Abstract: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

Abstract: A fast propagation technique for use in CMOS circuits, whereby faster signal transition at an information carrying edge of a propagating signal is achieved at a cost of slower signal transition at the opposite edge. The technique of the present invention skews a size ratio of P-channel pull-up to N-channel pull-down transistors in the CMOS circuit to obtain much faster transition at one (rising or falling) edge of the signal and slower transition at the opposite edge. The fast propagation technique of the present invention is well suited for synchronous digital CMOS circuits such as synchronous RAMs.

Abstract: An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal.

Abstract: An integrated circuit chip with high level logic functions formed from a pass gate logic family. The logic for each logic book includes at least one pass gate. Each book has complementary outputs and a pseudo latch attached to its outputs. If the book is of one FET type, the pseudo latch is of the opposite type. Books are placed in the logic function such that the output pseudo latches redrive opposite logic levels on alternating stages of series-connected books.

Abstract: Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable active driver circuits are employed. These circuits eliminate essentially all of the resistance present in prior art passive connections.

Abstract: A bus line is divided into at least first and second bus segments that are coupled together via a precharge buffer, each segment seeing less effective RC than if segmentation were not present. The precharge buffer provides first and second output buffer lines (or segments) that are monitored and cross-coupled through the buffer such that each line is pulled-up or pulled-down substantially simultaneously to keep equivalent states in each. Feedback provided by the cross-coupling further hastens the process of bus pull down. Still further acceleration of the pulldown process can result by sensing bus pulldown at trip point that is higher than a conventional logic level trip point. Segmenting the bus and coupling the segments with a precharge buffer results in less equivalent RC being presented to each bus segment. Thus, effective shunt capacitance is reduced, allowing use of downsized transistors coupled to the output buffer lines to pull down the bus segments.

Abstract: In an output circuit for outputting an output signal having a given potential level in response to a potential level of an input signal wherein the output signal is permitted to be in high impedance state in response to a first potential level of a reset control signal having first and second potential levels, the output circuit comprises a second control circuit for outputting a second output control signal in response to the input signal at the time when the reset control signal has the second potential level and also for outputting a third output control signal at the time delayed by a first time counting from the outputting of the second output control signal, the second control circuit having a function to stop the outputting of the second output control signal in response to the change of the potential of the reset control signal from its second potential level to its first potential level and also a function to stop the outputting of the third output control signal substantially at the same time as the

Abstract: An asynchronous logic circuit has a plurality of input lines (I) connected both to an n-channel logic block (NL) and to a p-channel logic block (PL) which is inverse with respect thereto (split transistor switch logic), in which, both in response to a rising and to a falling edge of a request signal at a request input (REQ), valid output data can be produced at outputs (OUT1, OUT2) of the asynchronous logic circuit in each case before a signal change at a ready-message output (RDY). Advantages are in particular the low outlay on circuitry and the doubling of the throughput in comparison with a corresponding status-controlled asynchronous logic circuit.

Abstract: A word line driver circuit for use in a semiconductor memory device for driving a word line of the memory device to a word line driving voltage having a voltage level greater than that of a power supply voltage includes a control circuit and a word line driving circuit. The word line driving circuit includes a pull-up transistor which is connected in series between the word line driving voltage and the word line, a transfer transistor connected in series between a row decoding signal and the gate electrode of the pull-up transistor. The control circuit generates a transfer output signal which is applied to the gate electrode of the transfer transistor. In a first operating mode, the transfer output signal has a voltage level greater than the power supply voltage by an amount equal to the threshold voltage of the transfer transistor, and, in a second operating mode, the transfer output signal has a voltage level equal to the power supply voltage.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A zero-power wide OR gate for implementing the "sum" of the "sum of product terms" in a programmable logic device (PLD). The wide OR gate includes a single additional input transistor for each added "product term" input from a sense amplifier. The wide OR gate further includes circuitry to decouple the current supply from sense amplifiers turned on during sleep mode to limit power utilized. To increase operation speed, the wide OR gate utilizes a strong current source when sense amplifiers are all turned off to quickly pull up internal circuitry while utilizing a weak current source when sense amplifiers turn on to allow the sense amplifiers to more easily overcome the current supply. To further increase speed, the wide OR gate includes a threshold shifting transistor to shift the pull down threshold of the output inverter for when all sense amplifiers are turned off while shifting the threshold back for when a sense amplifier transitions to on.

Abstract: An input circuit having a CMOS component which outputs correct logical values without through-current flowing when a high level logic output signal V.sub.OH at TTL level is input thereto. The input circuit 1 comprises inverter 20 which outputs by logically inverting the input signals and through-current prevention circuit 21 which stops the flow of current to inverter 20 from power supply V.sub.CC. The through-current prevention circuit 21 comprises reference voltage generating circuit 10, inverters 12 and 13, and MOS transistors 11a, 11b, 14, and 15. The threshold value voltage of inverter 12 is set slightly lower than the high logic level output V.sub.OH at TTL level, and the threshold value voltage of inverter 20 is set lower than inverter 12.

Abstract: A VLSI chip is disclosed having reduced power dissipation. This is accomplished by limiting the output voltage swing at the output of off chip driver circuits by utilization of a control circuit to regulate the gate bias voltage of an NFET pull-up transistor coupled to the output of the driver circuit and by feeding back the output of the driver circuit to the control circuit.

Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

Abstract: A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

Abstract: A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. During the precharge clock phase, the circuits precharge the intermediate nodes to a high logic level. During the evaluation clock phase, each circuit is initially in the stand-by state, in which it monitors the logic level on its network node. If a substantial deviation from the high level towards the low level is detected, the circuit switches to the discharge state, in which it enforces that level change by connecting its network node to the low level. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards a low level, and their circuits in turn switch to the discharge state.

Abstract: An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor.

Abstract: A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.

Abstract: An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage having an output node and a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply. A first input stage activates the first output switching means of the output stage in response to one of the differential ECL signals, and a second input stage activates the second output switching means of the output stage in response to the other differential ECL signal. The first input stage includes a first input switching means for coupling a first resistive element between the first voltage supply and the output node of the output stage, and the second input stage includes a second input switching means for coupling a second resistive element between the first voltage supply and the second voltage supply.

Abstract: A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique "pulse catcher" circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line.

Abstract: An output circuit and a bus buffer semiconductor LSI circuit which have functions of high speed and low power consumption while suppressing generation of undershoot and ringing in an output signal. The output circuit includes a delay circut and a current injecting circuit. The current injecting circuit operates so that, when a voltage at an output terminal of the output circuit is changed from a first level to a second level lower than the first level, it supplies a current to an output terminal only for a period of time after the voltage of the output terminal reaches a predetermined level. As a result, the load driving capability of the output circuit can be made effectively small only for a period of time during which the current injection circuit supplies the current to the output terminal.

Abstract: A semiconductor logic circuit apparatus includes a plurality of logic circuits each including complementary field effect transistors, and a plurality bipolar transistors associated with the respective ones of the logic circuits. When any one of the outputs of the logic circuits becomes high, an associated bipolar transistor becomes conductive to cause an output terminal of the apparatus to be charged from a voltage supply. With all the outputs of the logic circuits being low, all of the bipolar transistors are non-conductive, and a current supply coupled between the output terminal and ground dicharges charge on the output terminal.

Abstract: In a GaAs IC using an E/R type DCFL circuit or E/D type DCFL circuit, a Schottky barrier diode is connected between the positive polarity power source of the DCFL circuit and a load element. A deterioration of switching speed is prevented even in case of using a power source voltage of 2 V in the GaAs IC. Addition of the Schottky barrier diode in a super buffer circuit to prevent a slow increase in output voltage in the circuit is also disclosed.