Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the result of the comparison; a second differential amplifier which compares the sizes of the first input signal and a reference voltage and outputs a second output signal as the result of the comparison; and a third differential amplifier which compares the sizes of the second input signal and the reference voltage and outputs a third output signal as the result of the comparison, wherein the first differential amplifier shares transistors, to which the first and second input signals are input, with the second and third differential amplifiers. The first differential amplifier operates only in a differential operation mode, and the second and third differential amplifiers operate only in a single operation mode.

Abstract: A system and method of reducing an effect of signal distortion from reflection on a transmission line include changing at least one of a pedestal voltage level on the transmission line and a signal threshold voltage level in a processor coupled to the transmission line, such that the pedestal voltage level and the signal threshold voltage level are not substantially equal after the changing, and such that the effect of signal distortion from reflection on the transmission line is reduced.

Abstract: A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

Abstract: Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus increases and the intervals between the bus lines decrease. In the bus driving circuits and methods, a portion of the bus lines are driven at a first time, and a portion of the bus lines are driven at a second time, subsequent to the first time, so as to reduce or eliminate crosstalk between adjacent bus lines.

Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.

Abstract: A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay unit. The two comparators convert a three-state digital signal on the transmission line into two two-state digital signals so that the logic circuit can understand. When a glitch occurs at the output of the logic circuit, also the output of the receiver, caused by the transitions on the output of one of the comparators and a first signal being sent to the other end of the transmission line reaching the logic circuit not at the same time, the glitch detector causes the programmable delay unit to adjust delay to the propagation path of the first signal to the logic circuit so as to eliminate the cause of the glitch.

Abstract: A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit therein. The pad circuit includes an input/output pin, a gain-adjustable output buffer, an input buffer and a signal feature detector. The method includes the steps as follows. A test signal is firstly issued from the core logic circuit to the gain-adjustable output buffer, while the test signal is then manipulated and outputted to an external device via the input/output pin. Next, a feedback test signal is fed into the input buffer from the external device, while a test result is realized according to a waveform feature of the feedback test signal. Finally, the gain of the gain-adjustable output buffer is adjusted according to the obtained test result.

Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Abstract: A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Abstract: An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prevents erroneous operation. After power is input, in a switching control part 110, a flip-flop X23 is reset, a level change of output signals s1-s5 of an input part 100 is detected by a NAND gate X21, and an output signal s9 of the flip-flop X23 is raised. In a switching part 120, when the signal s9 is at low level, output signals s10-s14 are held at high level, and when the signal s9 is at high level, the output signals s1-s5 of the input part 100 are output to an output part 130. Thus, the output signals are held after the power input, and after the input signal rises, the signal transfer function is started, so that the output of incorrect control signals can be prevented, and thereby erroneous operation of a printer can be prevented.

Abstract: A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

Abstract: The signal processing device comprises determining means to supply an output signal having a value representative of a time constant of a part of an input signal having an appreciably exponential form. The determining means comprise first integrating means to supply a first integration signal representative of integration of the input signal in two opposite directions for appreciably equal times. Extraction means connected to the first integrating means supply a value representative of a time constant as a function of the first integration signal. The process comprises integration and extraction steps to supply the value representative of a time constant.

Abstract: In order to enable a simple and cost-effective directly electrically isolated transmission of data signals, the data signals are superposed on a clock signal in an input stage and are transmitted to an output stage in a directly electrically isolated manner via a decoupling device. The clock signal on which the transmitted signals are superposed is filtered out in the output stage. Pulse shape alterations occurring in the signals because of the transmission or because of the filtering-out of the clock signal are compensated in the output stage so that filtered data signals are present at the output of the circuit configuration.

Abstract: One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals and the output of the inverter coupled to the output terminals. The input and output of an inverter are also coupled to each of the output terminals. Finally, a pair of inverters are connected in parallel with each other in opposite directions between the output terminals. In another embodiment, a pair of inverters are also coupled between a respective input terminal and a respective output terminal. However, the output of a respective inverter is coupled to each output terminal, and the inputs of the inverters are coupled to a voltage divider circuit connected between the output terminals.

Abstract: A flat group-delay low-pass filter includes a series element connected between an input terminal and an output terminal, and a shunt element with one end thereof grounded. Inductors define the series element, a parallel circuit including a capacitor and a series circuit including a resistor and a capacitor defines the shunt element. The flat group-delay low-pass filter thus eliminates the need for inserting a fixed attenuator to control the effect of reflections due to impedance mismatching between the filter and other components. The resulting flat group-delay low-pass filter and an optical signal receiver including the filter have very low manufacturing costs and component costs.

Abstract: A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer characteristic between the input and the output. A capacitive element has a first node coupled to the input of the non-inverting circuit and a second node arranged to receive the digital input signal. A resistive element is coupled between the input and the output of the non-inverting circuit. The re-referencing circuit further includes a transient correcting circuit having a first input coupled to a substantially DC level of the first logic environment, a second input coupled to a substantially DC level of the second logic environment, and an output coupled to the input of the non-inverting circuit. The transient correcting circuit applies transient DC differences between the two environments to cancel the effects of transients in the digital input signal.

Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

Abstract: A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to receive control signals from well pull circuits. The control signal keeps the third transistor off when the bus driver circuit is not enabled.

Abstract: A signal transmitter for transmitting digital logic signals and a complementary receiver, are disclosed. The signal transmitter comprises a plurality of signal drivers and at least one reference driver. The signal drivers transmit digital signals, while the reference driver transmits a constant signal representative of a digital HI or LO. The signal and reference drivers are interconnected so that any noise due to package and power supply interconnection impedances is present in all transmitted signals including any reference signals. At a receiver, the reference signal including noise is used to establish threshold levels for digital HI and LO signals. Because noise is common to all transmitted signals, the receiver is able to reduce the effects of the noise by comparing the plurality of received signals with the reference signal.

Abstract: An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and reliably detect input logic signals in the presence of overshoot or undershoot conditions. In a preferred embodiment, the source terminals of input transistors are biased such that the impact of overshooting or undershooting signals at the input terminal are drastically reduced.

Abstract: An input buffer circuit includes a plurality of paths having a different threshold voltage, respectively, a comparator for comparing an output value of the paths, a switch for determining operation of the input buffer circuit based on an output value of the comparator, and a latch coupled to the switch. The input buffer circuit and method for using same maintains a previous output value to improve a noise margin of the input buffer circuit and to improve the stability of input buffer circuit operation.

Abstract: A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).

Abstract: A differential-type data transmitter includes a differential amplifier pair (T1, T2, T4, T6, T8) having a plurality of transistors and receiving a pair of a first input signal and a second input signal. A load (T3, T5, T7) is connected to the differential amplifier pair. A detection circuit (T9, T10, I4, I5, I6, I7) connected to a junction between the differential amplifier pair and the load is operative for detecting whether or not the first and second input signals are outside a common-mode input voltage range with respect to the differential amplifier pair. A first output circuit (T12) connected to the detection circuit is operative for outputting a signal depending on an output signal from the differential amplifier pair. The signal outputted from the first output circuit is set to a given level when the detection circuit detects that the first and second input signals are outside the conmmon-mode input voltage range.

Abstract: In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor receives at its gate an external signal /EXT and the second P channel MOS transistor receives at its gate an inverted signal of an output enable signal OEM. In a data output period, the signal OEM attains to the "H" level and the second P channel MOS transistor is rendered conductive, and therefore, even when power supply potential Vcc lowers in the data output period, the output node can be sufficiently charged, and an internal signal /INT can be generated stably.

Abstract: An asynchronous self-adjusting circuit includes an input circuit receiving an input signal and providing an output signal. The input circuit starts to switch the output signal to a first logic level based on the level of the input signal reaching a falling edge adjustable trip point, and starts to switch the output signal to a second logic level based on the level of the input signal reaching a rising edge adjustable trip point. A control circuit dynamically and asynchronously adjusts the falling and rising edge adjustable trip points as a function of a previous value of the input signal to permit the asynchronous self-adjusting circuit to respond quickly to changes in the input signal without causing oscillation of the output signal by asynchronously controlling when the output signal is permitted to again switch logic states once the output signal switches logic states.

Abstract: A digital input circuit including a first digital buffer for receiving a digital data signal and for providing a first buffered digital data output, the first digital buffer having a first switching threshold voltage; a second digital buffer for receiving the digital data signal and for providing a second buffered digital data output, the second digital buffer having a second switching threshold voltage that is greater than the first predetermined switching threshold voltage; a selection circuit responsive to the first buffered digital data output and the second buffered digital data output for providing a selection circuit output that is a replica of the first buffered digital data output or the second buffered digital data output; and a flip-flop for receiving the selection means output and providing a flip-flop output that is indicative of the logical state of the digital data signal.

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired.

Abstract: A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a non-inverted input terminal of the operational amplifier and a signal ground so that the ringing cancel circuit is connected in parallel with the hold capacitor. The ringing cancel circuit is made up of a resistance and a capacitor connected in series with each other. With this arrangement, a high-speed, highly accurate, low power consumptive sample and hold circuit can be realized.