Abstract: An hysteresis input buffer includes a first CMOS inverter generating a node signal, a second CMOS inverter coupled to the first CMOS inverter, inverting the node signal from the first CMOS inverter, and producing an intermediate signal, and a hysteresis control circuit coupled to the second CMOS inverter, receiving the intermediate signal, and producing an output signal having a low level during a predetermined delay time and a high level after the predetermined delay time has elapsed.

Abstract: A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.

Abstract: An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors.

Abstract: A differential input circuit includes a first differential circuit of a current mirror type for generating a first differential voltage by using an input voltage and a reference voltage, a second differential circuit of a current mirror type for generating a second differential voltage having a phase opposite to that of the first differential voltage by using the input voltage and the reference voltage, and a third differential circuit for generating an output voltage corresponding to a difference voltage of the first and second differential voltages by using the first and second differential voltages. A first clamping circuit for clamping the first differential voltage is provided between the first and third differential circuits. A second clamping circuit for clamping the second differential voltage is provided between the second and third differential circuits.

Abstract: A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: A clamping circuit useful in reducing ringing on a transmission line is described. The clamping circuit includes a pair of transistors coupled between the transmission line and opposite terminals of a voltage source. An enable circuit monitors the transmission line for transitions, both low-to-high and high-to-low, and enables the transistors to be biased such that they connect the transmission line to the voltage source in the presence of ringing.

Abstract: A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal.

Abstract: An input circuit provided in a semiconductor integrated circuit, comprises an nMOS transistor having a source connected to an input node receiving a transmission signal, a drain connected to a first node and a gate connected to a reference potential, and a pMOS transistor having a source connected to a power supply voltage, a drain connected to the first node, a first inverter having an input connected to the first node and an output connected to an output terminal, and a second inverter having an input connected to the first node and an output connected to a gate of the pMOS transistor, so that when the nMOS transistor is turned on, the pMOS transistor is rendered off, whereby no steady input current flows.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: A driver circuit for supplying an electric current to a device having a pair of power FET's connected in series between the device and a power supply.

Abstract: Disclosed is an output signal buffer circuit of semiconductor memory devices comprises: a plurality of buffer groups each comprising a plurality of output buffers grouped into unit group, in which each output buffer comprises a pull up transistor and a pull down transistor connected between a power supply voltage and ground in series; driving means for sequentially driving respective buffer groups according to internal control signals; and control signal generating means for producing the internal control signals for sequentially driving said buffer groups to said driving means in accordance with an external control signal.

Abstract: The present invention provides a driver/receiver pair connected as a repeater circuit which simultaneously transmits and receives information on multiple connected transmission lines. Transceiver circuits are provided which are mirror images of one another to perform the repeater function of the present invention. Each transceiver in the repeater circuit includes a non-inverting buffer stage which produces a signal swing less than the typical Vdd to ground which is typical for common CMOS inverters. The limited swing provides a variable reference input to a differential receiver element. This receiver looks at the incoming signal, and the signal being transmitted from the repeater to determine if the incoming signal is logical "1" or logical "0". This is done on each side of the repeater since the actual voltage level on the wire at the repeater terminal is a composite of the signal received by the repeater and the signal being transmitted by the repeater.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: A circuit for operating a polyphase DC motor, such as the type having a plurality of "Y" connected stator coils, has circuitry for charging the coils at a rate which will reduce EMI and other noise, while maintaining an acceptable charge rate. The gate of a selected high side driving transistor is charged at a relatively high rate during a ramping phase. During the ramping phase, the gates of the selected transistor is charged to a voltage near the voltage needed to form a channel in the transistor for conduction. After the ramping phase, the gates are charged at a lesser rate in order to control the rate of charging of the stator coils to prevent noise.

Abstract: A microprocessor circuit is provided that allows the internal microprocessor clock speed to vary depending upon a register that can be programmed by software. In addition, the drive strength of the internal clock generator may similarly be varied by software programming. The programmer or user of the microprocessor may change the internal clock speed such that the microprocessor operates at a first frequency or at a second frequency depending upon the performance requirements. A lower frequency of operation may be selected for low power consumption and low EMI, while a higher frequency of operation may be selected for computational intensive and high performance applications.

Abstract: A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.

Abstract: A semiconductor integrated circuit comprises a signal input terminal, a power supply voltage terminal to which a power voltage is applied, a reference voltage terminal to which a ground voltage is applied, a first PMOS transistor having a drain, a gate connected to the signal input terminal, and a source connected to the power supply voltage terminal, a second PMOS transistor having a gate and a drain being mutually connected to each other, and a source connected to the drain of the first transistor, a third PMOS transistor having a gate connected to the drain of the second transistor, a source connected to the power supply potential terminal, and a drain connected to the drain of the first transistor, an NMOS transistor having a gate connected to the power supply voltage terminal, a drain connected to the drain of the second PMOS transistor, and a source connected to the reference voltage terminal, an internal circuit connected to the drain of the NMOS transistor, a first overvoltage absorption element, conn

Abstract: An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage.