Bus Or Line Termination (e.g., Clamping, Impedance Matching, Etc.) Patents (Class 326/30)
  • Patent number: 11190188
    Abstract: Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 30, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Min-Hyung Cho, Young-deuk Jeon, Seong Min Kim
  • Patent number: 11190185
    Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Eun Ji Choi, Jin Ha Hwang, Keun Seon Ahn, Yo Han Jeong
  • Patent number: 11181635
    Abstract: A liquid level detector has an ultrasonic sensor connected thereto by two signal lines. When a drive signal is output from a drive circuit, the drive signal is output via an impedance matching circuit, thereby transmission and reception signals on the signal lines flow as complementary level signals. A receiver circuit obtains an amplified signal by amplifying the transmission and reception signals with a differential amplifier circuit, and by cutting a same phase noise signal.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 23, 2021
    Assignee: DENSO CORPORATION
    Inventors: Takuya Koizumi, Hironori Iwamiya, Akihiro Konno
  • Patent number: 11158356
    Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Kwan Su Shon, Keun Seon Ahn, Yo Han Jeong, Eun Ji Choi
  • Patent number: 11152944
    Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: October 19, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Achal Kathuria, Pradeep Jayaraman
  • Patent number: 11152939
    Abstract: A semiconductor apparatus includes a calibration circuit and a main driver. The calibration circuit is configured to generate a first calibration code when set to have a positive offset and generate a second calibration code when set to have a negative offset complementary to the positive offset. The main driver is configured to set a resistance value of the main driver based on the first and second calibration codes.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11145355
    Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwapyong Kim, Hundae Choi, Junha Lee
  • Patent number: 11145383
    Abstract: Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Hyunui Lee
  • Patent number: 11139216
    Abstract: A system, method, and non-transitory computer readable medium are provided for tuning sensitivities of, and determining a process window for, a modulated wafer. The sensitivities for dies of the modulated wafer are tuned dynamically based on a single set of parameters. Further, the process window is determined for the modulated wafer from prior determined parameter-specific nominal process windows.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 5, 2021
    Assignee: KLA-TENCOR CORPORATION
    Inventors: David Craig Oram, Abhinav Mathur, Kenong Wu, Eugene Shifrin
  • Patent number: 11133038
    Abstract: Embodiments of a peak power management (PPM) circuit on a memory die are disclosed. The PPM circuit includes a first transistor and a second transistor arranged in parallel, wherein the first and second transistors each has a drain terminal electrically connected to a first power source and a second power source, respectively. The PPM circuit also includes a resistor having a first terminal electrically connected to respective source terminals of the first and second transistors. The PPM circuit further includes a first contact pad on the memory die, electrically connected to a second contact pad on a different memory die through a die-to-die connection. The PPM circuit also includes a third transistor with a drain terminal electrically connected to a second terminal of the resistor, and a source terminal electrically connected to the first contact pad.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: September 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Qiang Tang
  • Patent number: 11115763
    Abstract: A device includes a voltage source configured to selectively drive a first wire and a second wire with a first voltage level. The device further includes an adjustable current source configured to selectively discharge the first and second wire. The device further includes a control circuit configured to output data and power by way of the first and second wire by selectively coupling the first wire to the voltage source and the second wire to the adjustable current source such that, during a first time period, the first wire has the first voltage level and the second wire has a second voltage level. The data and power is output by also selectively switching the couplings of the first time period such that, during a second time period subsequent to the first time period, the first wire has the second voltage level and the second wire has the first voltage level.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 7, 2021
    Assignee: Advanced Bionics AG
    Inventors: R. Tissa Karunasiri, Jie Yan, Scott Kenneth Arfin, Don Banh
  • Patent number: 11115021
    Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tongsung Kim, Youngmin Jo, Jungjune Park, Jindo Byun, Dongho Shin, Jeongdon Ihm
  • Patent number: 11095287
    Abstract: Multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 17, 2021
    Inventors: Jia Di, Chandler Bernard
  • Patent number: 11087802
    Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11074959
    Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: James A. McCall, Christopher P. Mozak, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang
  • Patent number: 11068010
    Abstract: A current mirror circuit includes a current output terminal, a first transistor, a second transistor, and a digital-to-analog converter (DAC). The first transistor includes a first terminal coupled to a power rail, a second terminal coupled to a current source, and a third terminal coupled to the current source. The second transistor includes a first terminal coupled to the power rail, a second terminal coupled to the second terminal of the first transistor, and a third terminal coupled to the current output terminal. The DAC includes an output terminal coupled to the second transistor.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Allan Shill, Binan Wang
  • Patent number: 11062744
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 11057070
    Abstract: A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 6, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chen-Kang Lin, Hung-Yi Chang, Bing-Juo Chuang
  • Patent number: 11057038
    Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
  • Patent number: 11038413
    Abstract: A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor may, in response an assertion of a control signal, source current to the regulated power supply node. In response to initiating a charge cycle, a control circuit may assert the control signal. During an assertion of the control signal, the control circuit may adjust a slope of a transition of the control signal using a voltage level of the switch node.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 15, 2021
    Assignee: Apple Inc.
    Inventors: Giovanni Saccomanno, Bogdan-Eugen Matei, Fabio Ongaro
  • Patent number: 11024353
    Abstract: Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 1, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ankur Agrawal, Simarpreet Kaur
  • Patent number: 11024400
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 11005477
    Abstract: The present technology relates to a driver circuit, a control method therefor, and a transmission/reception system that enable implementation of a large amplitude signal output required for long distance transmission with low power consumption. The driver circuit includes: a current drive circuit that outputs a predetermined current; and a termination resistance circuit connected in parallel with the current drive circuit, in which the termination resistance circuit connects a termination resistance to a transmission line when the current drive circuit outputs a current, and disconnects the termination resistance from the transmission line when the current drive circuit does not output the current. The present technology can be applied to, for example, a driver circuit that outputs a signal to a long distance transmission line, and the like.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 11, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroki Kihara
  • Patent number: 11003386
    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
  • Patent number: 10999107
    Abstract: A voltage mode transmitter includes a first output terminal, a second output terminal, and a plurality switch-resistor units between the first output terminal and a first voltage source, between the second output terminal and the first voltage source, between the first output terminal and a second voltage source, and between the second output terminal and the second voltage source. Each switch-resistor unit includes a switch and a resistor connected in series. The switches of the switch-resistor units are controlled such that a common-mode voltage of a differential signal outputted at the first and second output terminals deviates from an average of voltages provided by the first and second voltage sources.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 4, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shih-Chun Lin, Ming-Hung Chien, Shu-Chin Chuang
  • Patent number: 10998904
    Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sundeep Ram Gopal Agarwal, Brian C. Gaide, Ramakrishna Kishore Tanikella
  • Patent number: 10996885
    Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
  • Patent number: 10998912
    Abstract: A digital-to-analog converter includes a first current source module configured to supply a current I1 to the digital-to-analog converter, a first switch control module configured to control connection or disconnection between each branch and a trans-impedance amplifier in the digital-to-analog converter based on a to-be-converted digital signal, where the current I1 supplied by the first current source module flows to the trans-impedance amplifier through a connected branch, and the trans-impedance amplifier is configured to convert the current I1 supplied by the first current source module into an analog voltage and output the analog voltage.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 4, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chenlong Hou, Yuemiao Di
  • Patent number: 10991446
    Abstract: An electronic device includes a memory device including first and second ranks, and a system-on-chip that exchanges data with the memory device. The system-on-chip loads a first training code to the first rank and performs a first training operation on the second rank using the first training code loaded to the first rank, and loads the first training code to the second rank and performs a second training operation on the first rank using the first training code loaded to the second rank. The system-on-chip generates a first reference voltage for sampling output data of the first rank, and generates a second reference voltage for sampling output data of the second rank. The first and second reference voltages are generated based on a first result of performing the first training operation on the second rank, and a second result of performing the second training operation on the first rank.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yongseob Kim
  • Patent number: 10985759
    Abstract: An example apparatus includes a line driver and an interface circuit. The line driver has a plurality of source-series terminated (SST) driver segments including switching circuitry to selectively switch among at least three voltage-reference levels to drive an output node, common to each of the SST driver segments, in response to received digital signals by switching at a rate that is faster than a baud rate characterizing the received digital signals. The interface circuit drives a transmission link, in response to a drive signal at the output node, with an analog signal representing an oversampling of the received digital signals.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 20, 2021
    Assignee: NXP B.V.
    Inventors: Gerrit Willem den Besten, Niraj Kumar
  • Patent number: 10985757
    Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 20, 2021
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Bruce Millar
  • Patent number: 10978137
    Abstract: A memory device includes data receivers, voltage generators, and at least one pass gate. The data receivers include a first data receiver. The voltage generators is coupled to the data receivers and comprises a first voltage generator, in which the first voltage generator is configured to generate a first voltage signal for driving the first data receiver. The at least one pass gate is configured to be turned on under a first operation mode, to pass the first voltage signal generated from the first voltage generator of the voltage generators to at least one data receiver, other than the first data receiver, of the data receivers.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 13, 2021
    Assignee: NANY A TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 10957414
    Abstract: A method and a memory device for testing and repairing memory cells during a power-up sequence are provided. The memory device includes a built-in self test (BIST) unit for testing a memory cell array during the power-up sequence. The BIST unit performs a test on the memory cell array in response to a power stabilization signal, or performs a test on the memory cell array in response to an impedance control (ZQ) calibration command. The BIST unit terminates a test being performed in response to a write leveling command, or terminates a test being performed in response to an active command.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 23, 2021
    Inventors: Youngman Ahn, Sangyeol Lee, Jonggeon Lee
  • Patent number: 10951441
    Abstract: An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ‘ON’ and thereby DC-couple the input to the receiver, and cause the bypass switch to switch ‘OFF’ and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an ‘OFF’ state of the bypass switch while the input is AC-coupled.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: A Santosh Kumar Reddy, Sumanth Chakkirala, Sunil Rajan
  • Patent number: 10952000
    Abstract: Systems and processes are provided to detect an balanced audio signal and generation of an unbalanced audio signal including a first audio input for receiving a first audio signal, a second audio input for receiving a second audio signal, a processor for determining a first root mean square value for the first audio signal, a second root mean square value for the second audio signal and a combined root mean square value for a sum of the first audio signal and the second audio signal, the processor being further operative to generate an unbalanced audio signal in response to the first root mean square value exceeding a first threshold value, the second root mean square value exceeding the first threshold value and the combined root mean square value being less than a second threshold value, and an audio decoder operative to decode the unbalanced audio signal.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 16, 2021
    Assignee: SLING MEDIA PVT LTD
    Inventors: Nishit Dabi, Abhiroop Boggavarapu, Deepak Poongundran, Narayana Rao
  • Patent number: 10938392
    Abstract: A transmitter includes a driver circuit configured to drive a channel connected to a first node by controlling a turn-on impedance of a pull-up path, a turn on impedance of a pull-down path, or both according to a plurality of control signals; an encoder configured to generate the plurality of control signals according to a multi-bit data and a calibration signal; and a calibration circuit configured to generate the calibration signal including calibration information corresponding to the plurality of control signals, wherein the encoder determines activation and magnitude of each of the plurality of control signals according to the multi-bit data and the calibration information.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 2, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Yongun Jeong, Suhwan Kim
  • Patent number: 10929319
    Abstract: A data storage device can employ a front end bus to optimize data storage performance. A first controller may be connected to a first memory via a first bus and to a second memory via a second bus with the first bus and first memory housed within an internal cavity of an enclosure while the second bus is exposed to an exterior surface of the housing and the second memory is separated from the internal cavity. The first controller can be configured to substitute the second memory for the first memory in response to a front end controller identifying a type of data storage of the second memory.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 23, 2021
    Assignee: Seagate Technology LLC
    Inventor: Christopher Nicholas Allo
  • Patent number: 10931281
    Abstract: The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 23, 2021
    Assignee: SPRYNGS
    Inventors: Nicolas Pierre Delorme, Christophe Le Blanc, Daniel Saias
  • Patent number: 10916279
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Patent number: 10897253
    Abstract: A system may include: a first memory device; a second memory device; a third memory device; and a fourth memory device, wherein the first memory device to the fourth memory device are configured to share a resistor for impedance matching, wherein the first memory device to the fourth memory device are coupled to have a chain shape, wherein the forth memory device generates a completion signal when performance is completed and the first memory device receives the completion signal provided from the fourth memory device.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Oung Sic Cho, Jong Hoon Oh
  • Patent number: 10896143
    Abstract: A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert Wimmer, Taylor Loftsgaarden, Ming-ta Hsieh
  • Patent number: 10886898
    Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yasuo Satoh, Hiroki Takahashi, Shuichi Tsukada, Yuan He
  • Patent number: 10886918
    Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jason M. Johnson
  • Patent number: 10885950
    Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Kyung-Soo Ha, Young-Soo Sohn, Ki-Seok Oh, Chang-Kyo Lee, Jin-Hoon Jang, Yeon-Kyu Choi, Seok-Hun Hyun
  • Patent number: 10868519
    Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10862483
    Abstract: A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 8, 2020
    Inventors: Amedeo Paganini, Massimo Grasso, Sergio Morini, Davide Respigo
  • Patent number: 10846248
    Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
  • Patent number: 10825485
    Abstract: An apparatus is disclosed. The apparatus comprises a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Dean D. Gans, Larren G. Weber
  • Patent number: 10819382
    Abstract: A transceiver circuit includes a first port and second port configured to be coupled to a first and second transmission channel, respectively; a supply port configured to receive a supply voltage; a first transceiver and a second transceiver having signal ports connected to the first port and second port, respectively; and a control circuit coupled to the first and second transceivers. Each of the first and second transceivers is connected to the supply port. At least one of the first and second transceivers includes a first half-bridge and a second half-bridge connected to the supply port and to the signal port at least one of the first and second transceivers, and a transceiver output circuit configured to generate a transceiver output signal based on a voltages across a low-side switches of the first and second half-bridges.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 27, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Clemens Kain
  • Patent number: 10819447
    Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N?1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Frederick A. Ware, Richard E. Perego