Bus Or Line Termination (e.g., Clamping, Impedance Matching, Etc.) Patents (Class 326/30)
  • Patent number: 10360841
    Abstract: Providing a display device including a circuitry of multiple VBO inputs, which comprises: a circuit board includes a VBO output; a controlling board includes a plurality of VBO inputs; a plurality of first switches, each includes a controlling port interconnected to one of the VBO inputs of the controlling panel through a first resistor, each switch further includes a first connecting port connected to a power source through a second resistor, and a second connecting port is connected to a ground; and a second switch, includes a controlling port interconnected to each first connecting port of the plurality of first switches through a third resistor, and a first connecting port of the second switch connected to a power source through a forth resistor and to the VBO input of the circuit board, and a second connecting port is connected to a ground.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yu Wu
  • Patent number: 10353611
    Abstract: A data storage device includes a nonvolatile memory device; a control unit suitable for generating a descriptor in which works for controlling the nonvolatile memory device are described; a memory control unit suitable for performing a control operation for the nonvolatile memory device and a data input operation, based on the descriptor; and a calibrator suitable for performing a calibration operation for a signal to be provided to the nonvolatile memory device, in response to an enable signal provided from the memory control unit, wherein the memory control unit controls the calibrator such that the control operation for the nonvolatile memory device and the calibration operation of the calibrator are performed in parallel.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Yeob Chun
  • Patent number: 10347303
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Patent number: 10347358
    Abstract: A memory system includes: a buffer memory device; and a memory controller configured to communicate data with the buffer memory device, wherein the memory controller includes: an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage; and an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Jun Kim, Minsoon Hwang
  • Patent number: 10345836
    Abstract: An integrated circuit component receives an input signal via an external signal conduction path during a first interval and transmits an output signal via the external signal conduction path during a second interval. The integrated circuit component terminates the input signal and the output signal within one or more termination elements having an impedance in accordance with a characteristic impedance of the external signal conduction path to obviate signal termination within another integrated circuit component to which the output signal is destined and from which the input signal is sourced.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 9, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10348252
    Abstract: An amplifier circuit includes: a first inverter and a second inverter coupled in a cross-coupled form during an amplification operation and suitable for amplifying a voltage difference between a first line and a second line; a first isolation switch suitable for electrically connecting the first line and an output terminal of the first inverter to each other; a second isolation switch suitable for electrically connecting the second line and an output terminal of the second inverter to each other; and an equalizing switch suitable for electrically connecting the output terminal of the first inverter and the output terminal of the second inverter to each other, wherein before the amplification operation, a first offset compensation operation for turning on the second isolation switch and the equalizing switch and a second offset compensation operation for turning on the first isolation switch and the equalizing switch are performed.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 9, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Jung Min Yoon
  • Patent number: 10348271
    Abstract: An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 9, 2019
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Bo Hu, Kun Lan
  • Patent number: 10348270
    Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10340022
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10317242
    Abstract: A sensor device includes: a detection device that detects a predetermined physical quantity and converts the physical quantity into a detection signal; a communication device that is to be connected to a controller through a first line and a second line, performs at least one of reception from the controller or transmission to the controller by a differential transmission method and, based on a request signal received from the controller, transmits the detection signal generated by the detection device; and a conductive shield member that is applied with a constant potential and covers the detection device and the communication device. The conductive shield member reduces radiation noise generation and simplifies the sensor device structure.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 11, 2019
    Assignee: DENSO CORPORATION
    Inventors: Makoto Sakai, Tsuyoshi Uezono
  • Patent number: 10304503
    Abstract: A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Hae Kang Jung
  • Patent number: 10291229
    Abstract: A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 14, 2019
    Assignee: AnDAPT, Inc.
    Inventors: Kapil Shankar, Thomas Chan, Patrick J. Crotty, John Birkner
  • Patent number: 10283201
    Abstract: According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Inoue, Daisuke Arizono
  • Patent number: 10282340
    Abstract: A pin-configurable bus termination system may include a bus connector attached to an end of a bus. The bus connector may be configured for electrically connecting the bus to an input connector of a node. The node may include a bus termination resistance. The bus connector may include a first bus output pin, a second bus output pin and configurable first and second termination resistor pins. The configurable first and second termination resistor pins may be configurable to provide a first termination configuration and a second termination configuration. The first termination configuration may electrically interconnect the first and second bus output pins and the configurable first and second termination resistor pins to electrically connect the bus termination resistance for terminating the bus. The second termination configuration may include an open electrical circuit between the first and second bus output pins and the configurable first and second termination resistor pins.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 7, 2019
    Assignee: The Boeing Company
    Inventors: Todd B. Brouwer, Sean M. Ramey, Timothy E. Jackson, Edgar L. von Trotha, III
  • Patent number: 10282167
    Abstract: A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Dae Han Kwon
  • Patent number: 10269412
    Abstract: A memory system includes: a buffer memory device; and a memory controller including a data output driver configured to output data to the buffer memory device, wherein the data output driver includes: a pull-up switching unit coupled to an input/output power voltage, the pull-up switching unit including a PMOS transistor controlled by a data signal that varies according to the output data; a pull-up resistor unit including an NMOS transistor coupled to a DQ pad; a pull-down switching unit controlled by the data signal; and a pull-down resistor unit coupled to the pull-down switching unit.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Jun Kim, Minsoon Hwang
  • Patent number: 10271420
    Abstract: An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB) with a first signal path and a second signal path therein, a first finger disposed on the first signal path, a second finger disposed on the second signal path, a controller disposed on the PCB and coupled to a first memory via the first finger and to a second memory via the second finger, and a damping device disposed on the second signal path. The first and second signal paths share a common segment between the controller and a branch point on the PCB. The damping device is disposed between the second finger and the branch point. The distance between the first finger and the branch point within the first signal path is smaller than the distance between the second finger and the branch point within the second signal path.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 23, 2019
    Assignee: MEDIATEK INC.
    Inventors: PoHao Chang, Chun-Wei Chang
  • Patent number: 10243598
    Abstract: A system for integrated self-interference cancellation, comprising a transmit coupler, coupled to a transmit signal, that samples the transmit signal to create a sampled transmit signal; an analog self-interference canceller, coupled to the transmit coupler, comprising a controller; a signal divider, that splits the sampled transmit signal into a set of signal components; a set of phase shifters, wherein a phase shifter of the set shifts a signal component of the set of signal components by a total phase shift value; a set of scalers, wherein a scaler of the set scales the signal component by a total scale factor; a signal combiner, that combines the set of signal components into a self-interference cancellation signal; and a receive coupler, coupled to a receive signal, that combines the self-interference cancellation signal with the receive signal to remove a portion of self-interference present in the receive signal.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Kumu Networks, Inc.
    Inventors: Wilhelm Steffen Hahn, Alfred Riddle, Ernie Landi
  • Patent number: 10229746
    Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10224925
    Abstract: A communication node is connected to a transmission line which transmits a differential signal changeable between a high level and a low level and has a high potential signal line and a low potential signal line as a pair of signal lines. The communication node includes: an inter-line potential detector that detects an intermediate potential between the pair of signal lines; a node potential detector that detects an intermediate potential of an operation power source voltage which is supplied to the communication node; and a voltage adjuster that detects a difference between the intermediate potential detected by the inter-line potential detector and the intermediate potential detected by the node potential detector, and adjusts the operation power source voltage in accordance with the difference.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 5, 2019
    Assignees: DENSO CORPORATION, SOKEN, INC.
    Inventors: Hiroyuki Mori, Takuya Honda, Tomohisa Kishigami, Hirofumi Isomura
  • Patent number: 10223311
    Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Yeon Doo, Tae Young Oh
  • Patent number: 10224928
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die impedance calibration. A calibration circuit determines a digital compensation value for an input/output driver. A calibration adjustment circuit provides a digital compensation value to a calibration circuit to produce an analog output corresponding to the digital compensation value. A feedback circuit provides an analog output as feedback to a calibration circuit to produce an analog compensation value.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 5, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shiv Harit Mathur, Ramakrishnan Subramanian, Nitin Gupta
  • Patent number: 10209723
    Abstract: A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 19, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yu-Hsiang Huang, Jyun-Yang Shih, Chun-Chia Chen
  • Patent number: 10205451
    Abstract: Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistor, and a chip including a driver impedance calibration circuit configured to determine an impedance of the driver based on an impedance of the resistor. During a calibration operation, the driver impedance calibration circuit is configured to adjust an impedance code that controls an impedance of the driver to provide a next impedance code based on a comparison of a driver output voltage with a reference voltage. An adjustment step size of the impedance code is determined based on a value of the impedance code.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: February 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jason M. Johnson
  • Patent number: 10205431
    Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woon Kang, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10198014
    Abstract: A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Kapil Kumar Tyagi, Nitin Gupta
  • Patent number: 10193444
    Abstract: There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 29, 2019
    Assignee: PIXART IMAGING INC.
    Inventor: Lien-Sheng Wei
  • Patent number: 10193552
    Abstract: The termination resistor calibration circuit and a control method thereof are provided. The resistance of the termination resistor of the CML transmitter is directly calibrated, so that the error caused by duplicating the resistor can be avoided, which improves the calibration accuracy. In addition, no duplicated resistor and constant current source is required, which reduces the area occupied by the circuit. Further, the absolute current and the relative current are obtained from the bandgap module and thus have high accuracy. The output signal control module, the constant current source, and the termination resistors of the CML transmitter can be used for transmitting signals after the resistance calibration is finished, which improves the utilization of the circuit module.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 29, 2019
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Xiangyu Ji, Cheng Tao, Yu Chen, Xi Xu, Jiaxi Fu
  • Patent number: 10192607
    Abstract: According to various aspects, a memory controller may schedule ZQ commands to periodically calibrate individual memory ranks in a multi-rank memory. The memory controller may schedule a ZQ short command at each ZQ interval and record that the ZQ short command was missed with respect to a memory rank in a self-refresh mode at the ZQ interval. After the missed ZQ short commands reaches a first threshold, a ZQ long command may be scheduled at the next ZQ interval and normal ZQ behavior may resume in the event that the memory rank exits the self-refresh mode and the ZQ long command is executed. However, if the memory rank stays in the self-refresh mode until missed ZQ long commands reaches a second threshold, the memory controller may trigger a ZQ long command once the memory rank exits the self-refresh mode and skip a next ZQ calibration before resuming normal ZQ behavior.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Liyong Wang
  • Patent number: 10187052
    Abstract: Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 10187227
    Abstract: A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 22, 2019
    Assignee: Sony Corporation
    Inventor: Takanori Saeki
  • Patent number: 10164636
    Abstract: Embodiments of the present invention provide a level converter circuit with a resistor and a current adjustment circuit. The resistor is connected between an input and an output of the level converter circuit. The current adjustment circuit is configured to influence a current through the resistor such that an output voltage of the level converter circuit does not exceed a maximum allowable value.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Jan Sundermeyer, Norbert Weber
  • Patent number: 10164633
    Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 25, 2018
    Assignee: Invensas Corporation
    Inventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
  • Patent number: 10164634
    Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Yo Han Jeong
  • Patent number: 10158362
    Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 18, 2018
    Assignee: INTEL CORPORATION
    Inventor: Luke A. Johnson
  • Patent number: 10157651
    Abstract: A semiconductor device may include an input/output block suitable for operating by using a first voltage in an input mode and a second voltage in an output mode, a common input/output line coupled to the input/output block, and a voltage level maintaining block suitable for driving the common input/output line to maintain a voltage level of a transmission signal by using the first voltage in the input mode and the second voltage in the output mode.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: December 18, 2018
    Assignee: SK Hynix Inc.
    Inventor: Min-Sik Han
  • Patent number: 10153611
    Abstract: An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 11, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dacheng Zhou, Daniel Alan Berkram, Zhubiao Zhu
  • Patent number: 10146900
    Abstract: Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Satyanarayana Sahu, Renukprasad Shreedhar Hiremath, Radhika Vinayak Guttal
  • Patent number: 10148308
    Abstract: An auxiliary channel transceiving circuit includes: a first node and a second node; a first voltage-dividing circuit for generating a first received signal according to a signal from the first node; a second voltage-dividing circuit for generating a second received signal according to a signal from the second node; a first receiver amplifying circuit for amplifying the first received signal to generate a first amplified signal; a second receiver amplifying circuit for amplifying the second received signal to generate a second amplified signal; a comparison circuit for comparing the first amplified signal with the second amplified signal to generate a received signal; a first transmitter amplifying circuit for generating a first output signal according to a transmitting signal; and a second transmitter amplifying circuit for generating a second output signal according to the transmitting signal. The auxiliary channel transceiving circuit is not required to cooperate with traditional capacitors.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: December 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chun-Hao Lai
  • Patent number: 10134462
    Abstract: A semiconductor integrated circuit is described. A. transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about ½ of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 10128841
    Abstract: A termination circuit, a receiver and associated terminating method are provided. The termination circuit is applied to a receiving terminal for receiving a channel transmission signal. Being coupled to a control module, the termination circuit includes an upper circuit and a lower circuit. The upper circuit selectively conducts the receiving terminal to a first voltage terminal, and the lower circuit selectively conducts the receiving terminal to a second voltage terminal. The control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first switching signal and the second switching signal for a termination duration. The termination duration is corresponding to an n-th data bit carried by the channel transmission signal.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventor: An-Siou Li
  • Patent number: 10122362
    Abstract: In some examples, a device includes level-shifter circuitry and biasing circuitry including at least four diodes, wherein each diode of the at least four diodes is electrically connected in series. The biasing circuitry further includes push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal. The biasing circuitry is configured to deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes. The biasing circuitry is further configured to deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Giacomo Cascio, Giuseppe Bernacchia, Adriano Sambucco
  • Patent number: 10120406
    Abstract: An adaptive mode has been added in a common mode (CM) dimmer circuit to increase output current capability only when needed. Without having an adaptive mode in the CM dimmer, the output current drivers must operate with large quiescent current to handle a bulk current injection (BCI) event. Therefore, a CM dimmer without the adaptive mode will consume a significant amount of power even when there is no BCI event occurring. With the adaptive mode, the CM dimmer can be used effectively to suppress the BCI event, e.g., in a transformer-less physical layer (PHY) connection, while consuming minimal power during normal circuit operation.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 6, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Tony Susanto, Maarten Kuijk
  • Patent number: 10110225
    Abstract: An input/output (I/O) circuit for an integrated circuit includes an input-output terminal, a termination circuit and an impedance compensation circuit. The termination circuit includes a node that is coupled to the input-output terminal. The termination circuit exhibits substantially constant first impedance below a first frequency of signals received at the input-output terminal. Furthermore, the termination circuit exhibits second impedance that is less than the first impedance when signals having a second frequency that is higher than the first frequency are received at the input-output terminal. The impedance compensation circuit is coupled to the input-output terminal. The impedance compensation circuit compensates for differences between the first and second impendences when the signal having the second frequency that is higher than the first frequency is received at the input-output terminal.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 23, 2018
    Assignee: Altera Corporation
    Inventors: Ker Yon Lau, Tat Hin Tan, Choong Kit Wong
  • Patent number: 10103727
    Abstract: A power switch circuit includes a first input voltage, a first switch element, a switcher, a first bootstrap capacitor, and a second bootstrap capacitor. The first switch element includes a first control end, a first input end, and a first output end. The first input end is coupled to the first input voltage. The first output end provides an output voltage. The switcher is coupled to the first switch element. The first bootstrap capacitor is coupled to the switcher and provides a first driving voltage. The second bootstrap capacitor is coupled to the switcher and provides a second driving voltage. The first bootstrap capacitor and the second bootstrap capacitor alternately supply the first driving voltage or the second driving voltage to the first control end through an operation of the switcher.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 16, 2018
    Assignee: uPI Semiconductor Corp.
    Inventors: Chih-Wen Hsiao, Wen-Chieh Tsai
  • Patent number: 10090936
    Abstract: There is disclosed herein a circuitry system comprising first and second IC chips, configured or configurable such that; the first IC chip has an output terminal connected to receive an output signal from an output-signal unit of the first IC chip, the output-signal unit being connected between high and low voltage-reference sources of the first IC chip, the high and low voltage-reference sources being connected to respective high and low voltage-reference terminals of the first IC chip; and the second IC chip has an input terminal connected in a potential-divider arrangement between high and low voltage-reference terminals of the second IC chip, wherein: the high and low voltage-reference terminals of the first IC chip are respectively connected to the high and low voltage-reference terminals of the second IC chip; and the output terminal of the first IC chip is connected to the input terminal of the second IC chip.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 2, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Ian Juso Dedic
  • Patent number: 10091032
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Patent number: 10079604
    Abstract: An apparatus comprises multiple impedances and multiple pairs of transistors. Each pair connects to an impedance. Each pair includes high and low side transistors. The high side transistors and the low side transistors are connected each other and to a first terminal of the corresponding impedance, wherein second terminals of the impedances are connected to each other. The apparatus also comprises a staggered signal transistor driver to assert separate delayed high side signals to control inputs of the high side transistors. The delayed high side signals are time delayed with respect to each other. The driver asserts separate delayed low side signals to control inputs of the low side transistors.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 18, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Johan Tjeerd Strydom
  • Patent number: 10075165
    Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 11, 2018
    Assignee: SK hynix Inc.
    Inventors: Oung Sic Cho, Jong Hoon Oh
  • Patent number: 10068633
    Abstract: An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a chip section signal and command/address signals. The second semiconductor device may be configured to enter a power-down operation based on the chip section signal and the command/address signals. The second semiconductor device may be configured to interrupt input of a first group of the command/address signals during the power-down operation. The second semiconductor device may be configured to selectively perform an on-die termination (ODT) operation according to a level combination of a second group of the command/address signals.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 4, 2018
    Assignee: SK hynix Inc.
    Inventors: Kihun Kwon, Jaeil Kim