Bus Or Line Termination (e.g., Clamping, Impedance Matching, Etc.) Patents (Class 326/30)
  • Patent number: 10846248
    Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross, Randall J. Rooney
  • Patent number: 10825485
    Abstract: An apparatus is disclosed. The apparatus comprises a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Dean D. Gans, Larren G. Weber
  • Patent number: 10819382
    Abstract: A transceiver circuit includes a first port and second port configured to be coupled to a first and second transmission channel, respectively; a supply port configured to receive a supply voltage; a first transceiver and a second transceiver having signal ports connected to the first port and second port, respectively; and a control circuit coupled to the first and second transceivers. Each of the first and second transceivers is connected to the supply port. At least one of the first and second transceivers includes a first half-bridge and a second half-bridge connected to the supply port and to the signal port at least one of the first and second transceivers, and a transceiver output circuit configured to generate a transceiver output signal based on a voltages across a low-side switches of the first and second half-bridges.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 27, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Clemens Kain
  • Patent number: 10819447
    Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N?1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Frederick A. Ware, Richard E. Perego
  • Patent number: 10812075
    Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Linda K. Sun, Maria Jose Garcia Garcia de Leon, Raul Enriquez Shibayama, Abraham Isidoro Munoz, Carlos Eduardo Lozoya Lopez
  • Patent number: 10797700
    Abstract: A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changkyo Lee, Dongkeon Lee, Jinhoon Jang, Kyungsoo Ha, Kiseok Oh, Kyungryun Kim
  • Patent number: 10761130
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice is controlled to switchably connect a driver output to either a high voltage level or a low voltage level via a resistor, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. A calibration procedure is disclosed herein to generate a lookup table for how to selectively connect circuit slices to supply voltages given a target output voltage.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Lawrence Choi, Greg Warwar
  • Patent number: 10756737
    Abstract: An OCD circuit includes a pull-up circuit, a pull-down circuit, a first and a second compensation circuit. The pull-up circuit is enabled in response to an input data. The pull-down circuit is enabled in response to the input data. The first compensation circuit is coupled to the pull-up circuit and configured to induce a first compensation signal to the pull-up circuit in response to a first decision signal. The second compensation circuit is coupled to the pull-down circuit and configured to induce a second compensation signal to the pull-down circuit in response to a second decision signal. The first decision signal and the second decision signal are generated in response to the input data.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 25, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chang-Ting Wu
  • Patent number: 10750610
    Abstract: A printed circuit board may include a controller socket, first and second sockets provided on a top surface, third and fourth sockets provided on a bottom surface, and first, second, and third branching points. The first branching point may be spaced apart from the controller socket by a first distance in a horizontal direction parallel to the top surface and may be electrically connected to the controller socket. The second branching point may be spaced apart from the first branching point by a second distance longer than the first distance and may be electrically connected to the first branching point, the first and third sockets. The third branching point may be spaced apart from the first branching point by a third distance longer than the first distance and may be electrically connected to the first branching point, the second and fourth sockets.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Ki Paek, KwangSoo Park, Heeju Kim
  • Patent number: 10747245
    Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Yasuo Satoh
  • Patent number: 10742108
    Abstract: A programmable decoder (201) includes a counter (204A) whose count value increases for each clock; an address decoder (205A) for converting the count value into an address; a storage (251A) storing a table defining data according to the address converted from the count value; and a latch unit (207) for latching the data according to the address output from the storage (251A). A variable driver (202) includes a plurality of MOS transistors (208), (209), (210). The latch unit (207A) has outputs connected to control electrodes of a plurality of MOS transistors (208), (209), (210). The table defines a plurality of data items in the table so that the driving force of the variable driver (202) increases with an increase of the count value. A counter (20A) updates the count value while the arm control signal is being activated.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jun Tomisawa, Akinori Nishizawa
  • Patent number: 10734041
    Abstract: A semiconductor apparatus includes a first chip and a second chip. The first chip provides a first termination control signal to the second chip and the second chip provides a termination resistance for the first chip based on the first termination control signal, when the first chip receives data.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Hae Kang Jung
  • Patent number: 10726884
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 10729002
    Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jun Liao, Xiang Li, Yunhui Chu, Jong-Ru Guo, James McCall
  • Patent number: 10727852
    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman
  • Patent number: 10715133
    Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Hideya Oshima, Dirk Robert Walter Leipold
  • Patent number: 10707757
    Abstract: There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 7, 2020
    Assignee: AUDIOWISE TECHNOLOGY INC.
    Inventor: Lien-Sheng Wei
  • Patent number: 10698009
    Abstract: A method of biasing and reading-out a passive resistive sensor structure having two excitation nodes and two readout nodes, comprises the steps of: a) determining a first state of a first capacitor corresponding to a first amount of charge biasing the sensor structure such that a biasing current flows through said first capacitor during a first time interval determining a second state of the first capacitor corresponding to a second amount of charge integrating or averaging the readout signal during a second time interval related to the first time interval, thereby obtaining an integrated or averaged readout signal determining the sensor readout signal based on the integrated or averaged readout signal and a change in state of the first capacitor.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Melexis Technologies SA
    Inventors: Johan L. Raman, Pieter Rombouts
  • Patent number: 10693460
    Abstract: Memory devices employ circuitry that may be used to adjust the output impedance. Embodiments describe herein relate to fuse-based adjustment circuitry that may be used to assist output impedance compensation such as ZQ calibration, and facilitate reduction in the dimensions and/or power consumption of the memory device.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Takahashi, Shuichi Murai
  • Patent number: 10693436
    Abstract: An impedance adjusting circuit includes: a first node coupled to a resistor; a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node; a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock; a first average voltage unit suitable for generating an average voltage of the first node; a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit; and a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 23, 2020
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Suhwan Kim, Joo-Hyung Chae, Deog-Kyoon Jeong
  • Patent number: 10692560
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Bill Nale
  • Patent number: 10684948
    Abstract: An apparatus and method for memory backup are disclosed as being operational at a memory module that includes a volatile memory device but which is devoid of a non-volatile memory device. The memory module can emulate operations of a non-volatile memory on the memory module while the memory module is devoid of such non-volatile memory.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 16, 2020
    Assignee: SANMINA CORPORATION
    Inventor: Paul Sweere
  • Patent number: 10685609
    Abstract: A liquid crystal display device is disclosed. The liquid crystal display device includes: a display unit; and first to n-th control units configured to control respective areas of the display unit, where n is an integer greater than or equal to 2, wherein: each of the first to (n?1)-th control units is provided with a unidirectional channel linking that control unit to a following one of the control units that is assigned a next greater ordinal number; the n-th control unit is provided with a unidirectional channel linking the control unit to the following, first control unit; and each of the control units, based on a state of that control unit and also on a link signal received from a preceding one of the control units, transmits a link signal to a following one of the control units and controls an associated one of the areas.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 16, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Osamu Teranuma
  • Patent number: 10679909
    Abstract: A system, method, and non-transitory computer readable medium are provided for tuning sensitivities of, and determining a process window for, a modulated wafer. The sensitivities for dies of the modulated wafer are tuned dynamically based on a single set of parameters. Further, the process window is determined for the modulated wafer from prior determined parameter-specific nominal process windows.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 9, 2020
    Assignee: KLA-TENCOR CORPORATION
    Inventors: David Craig Oram, Abhinav Mathur, Kenong Wu, Eugene Shifrin
  • Patent number: 10679717
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10680613
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Alexey Kostinsky, Nadav Bonen
  • Patent number: 10672436
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10666467
    Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye Jung Kwon, Seungjun Bae, Yongjae Lee, Young-Sik Kim, Young-Ju Kim, Suyeon Doo, Yoon-Joo Eom
  • Patent number: 10666258
    Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 26, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • Patent number: 10657009
    Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 19, 2020
    Assignee: Dell Products, L.P.
    Inventors: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan
  • Patent number: 10659040
    Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 19, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Chuan Luo
  • Patent number: 10649025
    Abstract: A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a second data strobe interface and output to the first data strobe interface by reusing the FFE path. The second loopback path conversely allows a test signal to be routed from the first data strobe interface to the second.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 12, 2020
    Assignee: Cavium, LLC.
    Inventors: David Da-Wei Lin, Edward Wade Thoenes
  • Patent number: 10651848
    Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventor: Huy Nguyen
  • Patent number: 10641823
    Abstract: An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 5, 2020
    Assignee: Photonic Technologies (Shanghai) Co., Ltd.
    Inventors: Ming Lu, Patrick Yin Chiang, Jianxu Ma, Rui Bai, Xuefeng Chen, Juncheng Wang
  • Patent number: 10637440
    Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 28, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Guansheng Li, Jun Cao
  • Patent number: 10629246
    Abstract: A data output buffer includes: a pull-up pre driver configured to output pull-up data by reversing received data, and output up-code for adjusting a swing width of the received data; a pull-down pre driver configured to output pull-down data by reversing the received data, and output a down-code for adjusting the swing width of the received data; a pull-up main driver configured to output first data having a value of logic high according to the pull-up data, and adjust a swing width of the first data according to the up-code; and a pull-down main driver configured to output second data having a value of logic low according to pull-down data, and adjust a swing width of the second data according to the down-code.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Hwang
  • Patent number: 10630210
    Abstract: An optocoupler based control circuit and a method thereof are disclosed. The control circuit comprises a first control branch, which includes a first control signal input terminal configured to receive a first OFF function control signal; a first optocoupler, wherein a primary side of the first optocoupler is coupled to the first control signal input terminal, and an output of a secondary side of the first optocoupler is configured to control a first power supplied to a motor driving circuit; a first primary side on/off control circuit connected to the primary side of the first optocoupler, and configured to periodically turn on and off the coupling of the primary side to the first control signal input terminal; and a first secondary side filter circuit connected to the secondary side of the first optocoupler, and configured to filter the output of the secondary side, and configured as a low pass filter having a cutoff frequency lower than an on/off frequency of the primary side.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Zhejiang Holip Electronic Technology Co., Ltd.
    Inventor: Xiaoran Xu
  • Patent number: 10622086
    Abstract: An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Nak Kyu Park
  • Patent number: 10622029
    Abstract: A memory module includes a module board including a first and second data vias configured to transmit first and second data, respectively, through first and second data lines arranged adjacent to each other external to the module board, a plurality of layers including the first and second data vias passing therethrough, and a plurality of semiconductor memory devices arranged on at least one outer surface of the module board. The plurality of layers include first and second layers adjacent to each other. The module board includes a first data via wing extending from the first data via toward the second data via and not connected to the second data via in the first layer, and a seventh data via wing extending from the second data via toward the first data via and not connected to the first data via to overlap the first data via wing in the second layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Yeop Kim, Jae Jun Lee
  • Patent number: 10565151
    Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hyun Yoo Lee
  • Patent number: 10566987
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10566372
    Abstract: An analog signal bus driving circuit includes a plurality of signal sources, a plurality of signal output amplifiers, a plurality of shield drive amplifiers, and a time-division control circuit. The plurality of signal sources generate a plurality of analog signals. The plurality of signal output amplifiers output the plurality of analog signals to at least one signal line. The plurality of shield drive amplifiers output the plurality of analog signals to a shield line. The shield line extends along the at least one signal line to at least partially surround the at least one signal line. The time-division control circuit sequentially drives the plurality of signal output amplifiers in a time-division manner to sequentially output the plurality of analog signals in a time-division manner from the plurality of signal sources to the at least one signal line.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 18, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventor: Tohru Kanno
  • Patent number: 10559373
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10554234
    Abstract: A transmission device according to the disclosure includes a power supply section, a first transmitter, and a controller. The power supply section includes a voltage generator that generates a power supply voltage, and a load section configured to be able to change a load current at the voltage generator. The first transmitter has a first operation mode and a second operation mode, and transmits a first signal on the basis of the power supply voltage. The controller controls an operation of the load section when an operation mode of the first transmitter transitions between the first operation mode and the second operation mode.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: February 4, 2020
    Assignee: Sony Corporation
    Inventors: Takahiro Shimada, Hiroaki Hayashi
  • Patent number: 10530613
    Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Jason Johnson
  • Patent number: 10530324
    Abstract: Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Gubo Huang, Xiaobao Wang, Andrew Tabalujan, Sing-Keng Tan
  • Patent number: 10528493
    Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, George R. Zettles, IV
  • Patent number: 10522203
    Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hae Kang Jung
  • Patent number: 10498300
    Abstract: An IC for power conversion includes bias circuitry that generates one or more bias voltages. An adaptive biasing circuit adaptively shifts an input signal having a negative value to a positive value. An operational transconductance amplifier (OTA) receives a supply bias current and the first and second bias voltages. The OTA has first and second input terminals coupled to the input signal and ground, respectively. The OTA has first and second transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively. Additional circuitry of the OTA is coupled to the second internal node. The additional circuitry insures that the voltage at the second internal node follows the voltage at the first internal node. The OTA generates an output current signal responsive to a differential input voltage applied across the first and second input terminals.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 3, 2019
    Assignee: Power Integrations, Inc.
    Inventor: Frank Joseph Schulz
  • Patent number: 10491113
    Abstract: A switchable charge pump (SCP) combines a switching element and a charge pump. An SCP can be utilized within an RF circuit to allow the charge pump to be activated or deactivated in the circuit depending on incident RF power level. Multiple SCPs can be utilized to provide a generalized a single-pole N-throw (SPNT) system architecture. In one example, an RF transmit-receive (T/R) system utilizes SCPs to operate in one of three modes: transmit mode, receive mode, or self-selecting terminate mode.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 26, 2019
    Assignee: Raytheon Company
    Inventors: Claire E. Mooney, David D. Heston