Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract: Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.

Abstract: Apparatuses, systems, and methods for implementing a multi-driver architecture are described. The multi-driver architecture may include a first driver and a second driver configured to receive an input voltage. A predriver logic circuit may select one of the first driver and the second driver to convert the input voltage into an output voltage. A controller may be connected to the first driver and the second driver, and a switch may be connected between an output terminal of the first driver and the controller. The controller may be configured to control an internal resistance of the switch. In response to the first driver being selected by the predriver logic circuit, the first driver may output the output voltage at a constant impedance level.

Abstract: A semiconductor device includes a data input circuit suitable for receiving a training clock to provide first data signals and a strobe signal according to a plurality of input control signals in a training mode; a delay circuit suitable for outputting second data signals by delaying the first data signals according to delay values corresponding to respective setting codes; a data alignment circuit suitable for outputting third data signals by aligning the second data signals according to the strobe signal; a code generation circuit suitable for generating a preliminary code corresponding to the third data signals according to the training clock, and sequentially storing the preliminary code as the setting codes according to a code-lock signal; and a lock-detection circuit suitable for activating the code-lock signal based on the training clock and the preliminary code.

Abstract: A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output data strobe signals to accompany data from the volatile memory subsystem during a memory read operation and to output to accompany data strobes output by data buffers in response to data strobe signals from the memory controller during a system-initiated operation to transfer data from the NV memory subsystem to the volatile memory subsystem.

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

Abstract: A method and corresponding broadcast reception device that includes: an impedance matching circuit for adjusting an input impedance value of the broadcast reception device; and a control unit, wherein the control unit can control the impedance matching circuit so as to adjust the input impedance value to a predetermined reference impedance value when the mode of the broadcast reception device is a mode for receiving a broadcast signal through a cable, and control the impedance matching circuit so as to adjust the input impedance value to be less than the predetermined reference impedance value when the mode of the broadcast reception device is not the mode for receiving a broadcast signal through a cable.

Abstract: Provided is a drive circuit, including drive units, a pre-drive module, and a resistance value selection circuit. Pull-up resistors of the drive units are adjustable; the pre-drive module is connected to M drive units and controls the pull-up resistors of the M drive units and resistance values of the pull-up resistors through a drive control signal, the M being an integer greater than 1; the resistance value selection circuit is connected to the pre-drive module and configured to select one of a first code and a second code for outputting as a target code according to a selection signal; and the pre-drive module outputs the drive control signal according to the target code.

Abstract: Apparatuses, systems, and methods for memory initiated calibration. The memory includes a termination circuit with a tunable resistor and a calibration detection circuit with a replica tunable resistor. The calibration detection circuit measures a resistance of the replica tunable resistor and provides a calibration request signal if the resistance is outside a tolerance. Responsive to the calibration request signal, a controller of the memory schedules the memory for a calibration operation.

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: An integrated circuit, a control method, and a system are provided, to improve reliability of the integrated circuit. The integrated circuit mainly includes a power supply pin, a configuration pin, a switchable pull-up resistor, and a control unit. The integrated circuit can provide a control signal for a target chip using the configuration pin of the integrated circuit. In the integrated circuit, a first end of the switchable pull-up resistor is connected to the power supply pin, a second end of the switchable pull-up resistor is connected to the configuration pin, and a control end of the switchable pull-up resistor is connected to the control unit. The power supply pin can receive a power supply voltage of the integrated circuit.

Abstract: A semiconductor apparatus may include: a command generation circuit configured to generate a first internal command signal and a second internal command signal, which are sequentially activated on the basis of a data command signal for a data driving operation; an impedance setting circuit enabled on the basis of the first internal command signal, and configured to set impedance into which a reference resistance is reflected; and a data driving circuit enabled on the basis of the second internal command signal, and configured to perform the data driving operation on the basis of the set impedance.

Abstract: A semiconductor apparatus includes a calibration circuit, a selection circuit, and a data circuit. The calibration circuit generates a plurality of calibration signals by being coupled to a plurality of reference resistors. The selection circuit selects at least one signal among the plurality of calibration signals on the basis of an impedance setting signal. The data circuit sets an impedance based on the selected calibration signal.

Abstract: A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

Abstract: A driving circuit includes: a primary driver configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driver connected to an output terminal of the primary driver and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: On-die termination (ODT) is triggered through a serial signal encoding on an ODT signal line instead of a simple binary enable signal. An ODT circuit applies one of multiple termination impedances based on the ODT signal encoding. An ODT enable signal line receives an ODT enable signal as multiple serial bits to encode the selected termination impedance, to cause the ODT circuit to apply the selected termination impedance.

Abstract: A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

Abstract: An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Abstract: A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.

Abstract: A memory device includes a calibration circuit configured to perform a ZQ calibration operation according to a calibration command signal and a calibration power voltage, and a calibration control circuit configured to determine the calibration command signal based on a comparison result obtained by comparing the calibration power voltage level with at least one reference voltage level.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

Abstract: A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

Abstract: A termination circuit, including a termination resistor, a first switch circuit, a second switch circuit, and a control circuit, is provided. A first end of the termination resistor is coupled to a signal pad. A first end of the first switch circuit is coupled to a second end of the termination resistor. A first end of the second switch circuit is coupled to a second end of the first switch circuit. A second end of the second switch circuit is coupled to a reference voltage line. During a period when the second switch circuit is turned on, the control circuit turns on the first switch circuit with a bias voltage. During a period when the second switch circuit is turned off, the control circuit turns off the first switch circuit with a voltage of the first end of the first switch circuit.

Abstract: An apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

Abstract: There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.

Abstract: A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Abstract: A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

Abstract: An off chip driving system includes a decision circuit, multiple first and second adjustable-enhancement circuits, and multiple first and second drivers. The decision circuit outputs a first and a second decision signal according to a clock and an input data. Each first adjustable-enhancement circuit generates one of first control signals in response to the first and the second decision signal and one of first optional signals. Each second adjustable-enhancement circuit generates one of second control signals in response to the first and the second decision signal and one of second optional signals. Each first driver is coupled to the corresponding first adjustable-enhancement circuit and configured to be enabled in response to the corresponding first control signal. Each second driver is coupled to the corresponding second adjustable-enhancement circuit and configured to be enabled in response to the corresponding second control signal.

Abstract: An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

Abstract: A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

Abstract: An impedance calibration circuit includes first and second calibration circuits, a switch circuit and a control circuit. The first calibration circuit is coupled to an external resistance, and generates a first voltage. The second calibration circuit generates second and third voltages. The switch circuit is coupled to the first and second calibration circuits. The switch circuit selectively provides the first, second, and third voltages to first and second nodes. The control circuit is coupled to the first and second nodes. The control circuit generates first, second, and third control signals according to voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages respectively to the first and second nodes.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: A code shift calculation circuit is provided. A first operation circuit of the code shift calculation circuit generates a first output value according to a temperature difference and a first change rate of a driving strength code to temperature. The temperature difference is a difference between a previous temperature when getting a previous ZQ command and a current temperature when getting a current ZQ command. A second operation circuit generates a second output value according to a voltage difference and a second change rate of the driving strength code to voltage. The voltage difference is a difference between a previous working voltage when getting the previous ZQ command and a current working voltage when getting the current ZQ command. A third operation circuit sums up the first output value and the second output value to generate a shift value, thereby adjusting the driving strength code calibrated by ZQ calibration.

Abstract: A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

Abstract: A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor resistor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.