Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.

Abstract: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.

Abstract: An inverter with adjustable threshold and irrelative to voltage, temperature, and process is disclosed. The inverter includes an input end for receiving an input signal; an output end for outputting an inverted signal of the input signal; a first PMOS whose gate is coupled to the input end, drain is coupled to the output end, and the source is coupled to a power supply; a first NMOS whose gate is coupled to the input end, drain is coupled to the output end, and source is coupled to a ground end, and an adjustable current source coupled to the output end for providing current with adjustable size to the output end for adjusting threshold of the inverter.

Abstract: A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting circuit that has a current circuit connected to a power supply, said variable resistor that is connected between said current circuit and the ground and receives a main current output from said current circuit, a comparator circuit that compares the potential of the variable resistor with a first reference potential and outputs a signal, and a control circuit that controls the resistance of said variable resistor based on the output signal of said comparator circuit; and an additional current adjusting circuit that is connected between said power supply and said variable resistor and outputs an additional current to said variable resistor according to an external signal determined by the resistance of an external parasitic resistor between said term

Abstract: A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Abstract: An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.

Abstract: An impedance control system is composed of a target circuit having a controllable impedance; a replica circuit having a structure identical to the target circuit; a first binary counter providing the replica circuit with a first impedance control code indicative of a counter value of the first binary counter for controlling an impedance of the replica circuit; a comparator comparing a voltage received from the replica circuit with a reference signal; a second binary counter responsive to an output signal from the comparator for being counted up or down; and a control circuit extracting upper multiple bits out of a counter value of the second binary counter, and generating a second impedance control code indicative of the upper multiple bits. The impedance of the target circuit is controlled in response to the second impedance control code.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communicating thermal indicia of one or more of the devices in the shared bus system to a memory controller device. The memory controller includes an on-die termination control circuit for setting and resetting the enablement of the signal termination components of the one or more devices. In a preferred embodiment, the on-die termination control circuit sets and resets the enablement of the signal termination components in accordance with the determined thermal indicia.

Abstract: There is provided apparatus for connecting between a data source or a data receiver and a data line. The apparatus comprises an impedance and an impedance controller arranged to continually adjust the value of the active impedance so as to control the relative impedances of the total source, the total source comprising the data source and the impedance, and the data line or of the total receiver, the total receiver comprising the data receiver and the impedance, and the data line. There is also provided a semiconductor chip, connectable to a data line, the semiconductor chip comprising the apparatus together with a data source or data receiver, as appropriate. There is also provided a method for controlling impedance matching between a data source or data receiver and a data line.

Abstract: Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an offset feedback voltage are obtained. Differences between pairs of these voltages are differentially amplified to produce first and second bias voltages. Pull-up and pull-down voltages are driven partially responsive to the first bias voltage and the second bias voltage to provide first and second control voltages. The first control voltage may be provided to a first resistance for the driving of the first pull-up and pull-down voltages. The second control voltage may be provided to a second resistance for the driving of the second pull-up and pull-down voltages. The first control voltage and the second control voltage may be provided to a third resistance.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

Abstract: A compensation circuit is disclosed. The compensation circuit includes a driver stage having an output, a differential output device including a base coupled to the output of the driver stage, and a feedback block coupled to a first emitter of the differential output device. The differential output device includes a second emitter to provide a differential output, and the feedback block generates a feedback signal to adjust the differential output. The first emitter comprises a replicating transistor, and is proximate to the second emitter of the differential output device. By keeping the replicating emitter near the differential output device, the variances of temperature and process over the semiconductor die do not affect the performance of the compensation circuit. The compensation circuit may also compensate for variations in common-emitter current gain.

Abstract: A current limiter of an output transistor comprises an output transistor, a current detection transistor monitoring a current flowing through the output transistor, a current mirror circuit, a protection transistor outputting a current having passed through the current mirror circuit, the current being proportional to the monitored current and dependent on a voltage between a drain and a source or between a collector and an emitter of the output transistor and an input terminal connected to an output of the protection transistor.

Abstract: An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.

Abstract: To transmit a high-speed digital signal of several tens GHz via a differential line by connecting a differential line referring to the ground to differential lines not referring to the ground, there is provided a signal transmission system which transmits a digital signal between circuit blocks via a signal transmission line, each of the circuit blocks basically including a functional circuit, a reception/transmission circuit formed separately from the functional circuit and an impedance-matched transmission line (115) formed between reception and transmission ends of the reception/transmission circuit; a differential line (105) referring to the ground (110), led out from a differential output driver, being formed from differential signal lines disposed symmetrically with respect to the ground (110) in the circuit block, only differential pair lines (111, 112) not referring to the ground being extended directly from the differential signal lines disposed symmetrically with respect to the ground in the signal

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract: Disclosed is an on-die termination (‘ODT’) impedance calibration device. The ODT impedance calibration device comprises: a pulse generator for outputting a calibration signal of a pulse type for calibrating an ODT impedance; an M-bit counter for counting the number of pulses of the calibration signal; a first maximum counter trigger signal generator controlled by the M-bit counter; an N-bit counter for counting the number of pulses of the calibration signal; a second maximum counter trigger signal generator controlled by the N-bit counter; a delay unit for receiving a delay signal and outputting the delay signal after a predetermined period of time; an update trigger signal generator for outputting a pulse signal which is toggled according to an output signal of the delay unit; and an ODT impedance calibration unit for receiving the calibration signal and outputting a control signal for calibrating an ODT impedance.

Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Abstract: The present invention is a device and method to change the reflection time of a bidirectional signal so as to cause a false data value to be correctly seen as the proper data value when the bidirectional signal travels between a first semiconductor chip and a second semiconductor chip, through a transmission line between the two semiconductor chips. The reflection time is adjusted by coupling an electrical network to the transmission line to cause an early electrical reflection. In one embodiment, the network is coupled to establish an impedance discontinuity between the board trace and the package trace.

Abstract: According to one example embodiment, a buffer, e.g., in a clock/signal distribution apparatus is provided that substantially reduces jitter due to power supply noise. Decoupler and input stage isolates load from the top rail power supply (VDD). In a more particular embodiment, jitter contributions from the bottom rail power supply (VSS) can be minimized by cross-coupled load devices within load. Substantial independence from process and temperature is facilitated through the use of current bias, such as Proportional to Absolute Temperature (PTAT) current bias.

Abstract: An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.

Abstract: When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

Abstract: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.

Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

Abstract: An apparatus includes termination circuitry to terminate one or more lines. The termination circuitry draws a first current from a termination voltage supply through a termination voltage delivery network for each terminated line carrying a first signal. Partial current shunt circuitry draws a second current from the termination voltage supply through the termination voltage delivery network for each terminated line carrying a second signal. The first and second currents are distinct.

Abstract: A low voltage differential signal (LVDS) input circuit with extended common mode range has been disclosed. One embodiment of the LVDS input circuit includes a first resistor coupled between a differential logic circuit and a first input pad, a second resistor coupled between the differential logic circuit and a second input pad, and a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node. Other embodiments are described and claimed.

Abstract: A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a, 104b) and a reference input (106a, 106b). A first termination resistance (112) connects the signal inputs (104a, 104b) and a second resistance (114) connects the reference inputs (106a, 106b). A first termination resistance (116) connects the second signal input (104b) to the termination voltage (120) and a second termination resistance (118) connects the second reference input (106b) to the termination voltage (120). A first ratio between the first resistance (112) and the first termination resistance (116) corresponds to a second ratio between the second resistance (114) and the second termination resistance (118).

Abstract: An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data transmission line. The digital control loop stabilizes input/output impedance matching of various devices to within a precise ohmic range that is far narrower than standard process variations, such as sheet resistance, within the components themselves. The impedance matching circuit also overcomes EMI problems normally associated with digital control and thus provides dynamic on-chip digital control without non-linearity and with tighter tolerance than is presently possible. Accordingly, the circuit boosts performance of peripheral devices that communicate over a standard USB port, without the need for a computer as a go between or intermediate interface. This makes device to device communication possible as between USB On-the-Go capable devices.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.

Abstract: Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

Abstract: In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

Abstract: Termination circuitry is to terminate one or more lines and is to draw current from a termination voltage supply and through a termination voltage delivery network. Partial termination voltage current shunting may be used to help define a range of current variation through the termination voltage delivery network.

Abstract: A low voltage differential signal driver that generates a differential signal using a switching sequencer for ensuring uniform transitions of the output signals, and a driver that includes a network of matched resistors for generating the output signals. The network of matched resistors can be configured based on one or more sequencing signals generated by the switching sequencer.

Abstract: An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator develops a reference impedance based on a reference value. The impedance matching controller continually adjusts an input of the reference impedance generator to match the reference value within a predetermined tolerance. Each output impedance generator is coupled to a corresponding output and is controlled by an output impedance control input. The programmable bias controller combines a bias amount with the value of the input of the reference impedance generator to provide the output impedance control input. The bias controller is programmable to provide a bias amount to compensate for any process variations between the reference impedance generator and each output impedance generator.

Abstract: An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which sensesthe signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments.