Signal Level Or Switching Threshold Stabilization Patents (Class 326/31)
  • Patent number: 10404265
    Abstract: An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventors: Brendan Farley, Bruno Miguel Vaz, Darragh Walsh
  • Patent number: 10378967
    Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 13, 2019
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Frederick A. Ware
  • Patent number: 10320370
    Abstract: Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 11, 2019
    Assignee: MoSys, Inc.
    Inventors: Prashant Choudhary, Haidang Lin, Alvin Wang, Saman Behtash, Shaishav Desai
  • Patent number: 10270444
    Abstract: According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 23, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Edward James Luckett, Christopher Allan Poirier
  • Patent number: 10218492
    Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 10014850
    Abstract: The present invention provides a driving stage circuit, including a driving switch circuit and a conduction resistance adjusting circuit. The driving switch circuit generates an output signal according to a switch control signal. The conduction resistance adjusting circuit clamps the switch control signal to a first clamping level according to a current flowing through the driving switch circuit when the current is higher than a first current threshold, such that the conduction resistance of the driving switch circuit is not smaller than a first resistance so that a short circuit current of the driving switch circuit is not larger than a short circuit current limit, wherein a lowest level of the conduction resistance of the driving switch circuit is smaller than a second resistance and the output voltage level does not exceeds a output voltage limit when the current is lower than the first current threshold.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 3, 2018
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Hsinlun Li
  • Patent number: 9874457
    Abstract: Systems and methods for estimating lifestyle metrics with a wearable electronic device are disclosed herein. One disclosed system may include the wearable electronic device comprising a processor and a sensor system providing inputs to the processor. The sensor system may include a high power sensor and a low power sensor. The processor may operate in a high power mode in which both sensors are operational and a low power mode in which the high power sensor is not operational. In the high power mode, the processor may compute a lifestyle metric about a user for a first time period based on first data from the high power sensor. In the low power mode, the processor may compute the lifestyle metric for a second time period based on second data from the low power sensor and the first data and/or a derivative of the first data.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 23, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Han Yee Mimi Fung, Haithem Albadawi
  • Patent number: 9800244
    Abstract: An inverter circuit includes a pull-up control circuit and a pull-up drive circuit. The pull-up control circuit generates a drive signal which is enabled during a first time period in response to an input signal and an output signal. The pull-up drive circuit drives the output signal to a power supply voltage in response to the input signal and the drive signal. The pull-up drive unit drives the output signal with a first drivability during the first time period and drives the output signal with a second drivability during a second time period.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 24, 2017
    Assignee: SK hynix Inc.
    Inventors: Jung Ho Lim, Jung Hwan Ji
  • Patent number: 9621136
    Abstract: A data sampler circuit comprises a transconductance amplifier, a latch circuit, a current-to-voltage converter, and a negative resistance circuit. The transconductance amplifier has an input and an output. The latch circuit is coupled to the output of the transconductance amplifier. The current-to-voltage converter has an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit. The negative resistance circuit is coupled to the output of the transconductance amplifier and provides equalization during both a sampling mode and a data latching mode. In one embodiment, the negative resistance circuit comprises a pair of cross-coupled transistors. A gain of the negative resistance circuit can be adjusted based on a pulse width of an input signal.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: April 11, 2017
    Assignee: NXP USA, INC.
    Inventor: Kevin Yi Cheng Chang
  • Patent number: 9584222
    Abstract: A driving circuit for an optical modulator is disclosed. The driving circuit includes a differential amplifier and a DC-level equalizer. The differential amplifier amplifies a differential input signal consisting of a positive-phase signal and a negative-phase signal, and outputs a driving signal to the optical modulator. The DC-level equalizer superposes two bias levels to the positive-phase and negative-phase signals respectively, and adjusts the bias levels thereof to equalize respective peak or bottom levels of the positive-phase and negative-phase signals.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 28, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Taizo Tatsumi
  • Patent number: 9559588
    Abstract: A power managing apparatus, a DC-DC control circuit, and a method for enabling a chip are disclosed. The power managing apparatus has an enable pin and the enable pin is used to couple a first level control circuit. The power managing apparatus includes a second level control circuit and a level detecting circuit. The second level control circuit is coupled to the enable pin. The level detecting circuit is coupled to the enable pin and used to detect a control signal on the enable pin. The control signal is transmitted from the first level control circuit. The control signal has at least three levels according to operations of the first level control circuit and the second level control circuit.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: January 31, 2017
    Assignee: UPI SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Ching Hsu, Yen-Hsun Wang
  • Patent number: 9461624
    Abstract: In one example, a method includes, in response to a voltage level of an input signal satisfying an input voltage threshold, activating a first driver of a plurality of drivers configured to collectively generate an output signal. In this example, the method also include, in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, toggling activation of a second driver of the plurality of drivers, wherein the second driver is configured to switch more current when activated than the first driver, and wherein the first driver has a faster slew rate than the second driver.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 4, 2016
    Assignee: Infineon Technologies AG
    Inventors: Soujanya Ravula Lakshmi, Madesh Umashankar
  • Patent number: 9412145
    Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 9, 2016
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Xavier Cauchy, Anthony Philippe, Isabelle Faugeras, Didier Siron
  • Patent number: 9379694
    Abstract: A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: June 28, 2016
    Assignee: NXP B.V.
    Inventor: Gerrit Willem den Besten
  • Patent number: 9342126
    Abstract: Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Son H. Lam, Joseph T. Dibene, II, Henry W. Koertzen, Steven D. Patzer
  • Patent number: 9213667
    Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hayden C Cranford, Jr., Daniel M Dreps, William R Kelly
  • Publication number: 20150145557
    Abstract: The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.
    Type: Application
    Filed: March 6, 2014
    Publication date: May 28, 2015
    Applicant: Amazing Microelectronic Corp.
    Inventors: Tang-Kuei TSENG, Chih-Hao CHEN, Szu-Hsien WU, Ryan Hsin-Chin JIANG
  • Patent number: 9007090
    Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8970283
    Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar
  • Patent number: 8947119
    Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 3, 2015
    Assignee: SK hynix Inc.
    Inventor: Dong Wook Jang
  • Publication number: 20150022235
    Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Inventors: Hideki UCHIKI, Satoru KISHIMOTO
  • Patent number: 8890566
    Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 18, 2014
    Assignee: Semtech Corporation
    Inventor: Daniel Kurcharski
  • Patent number: 8884645
    Abstract: An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after to the active enable signal is enabled.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 8887120
    Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Amit Kumar Dey, Amit Roy, Vijay Tayal
  • Patent number: 8861621
    Abstract: In a receiver circuit, a binary signal is generated based on a signal level of a received signal that has been received via a transmission line from a driver of a transmitter circuit. Then, a first stable state and a second stable state are detected based on a reference signal whose signal level changes in accordance with the received signal. In the first stable state, the received signal is stable at a first signal level. In the second stable state, the received signal is stable at a second signal level. When the first stable state is detected and the received signal is changed from the first signal level into the second signal level, the generated binary signal is retained at a signal level corresponding to the second signal level, until the second stable state is detected.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 14, 2014
    Assignee: Denso Corporation
    Inventors: Hiroyuki Mori, Naoki Kamikawa, Masayoshi Satake, Tomohisa Kishigami, Tomoyuki Koike
  • Patent number: 8856712
    Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 7, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Srikanth Bojja, Bhavin Odedara
  • Patent number: 8823413
    Abstract: A device for sensing a binary signal includes a device configured to measure a signal level of the signal, a device configured to determine whether the measured signal level is “low” or “high”, a device configured to provide a variable input impedance, and a device configured to control the input impedance in response to the measured signal level. The variable input impedance may be provided by way of a transistor and a resistor, and by controlling the duty ratio of the transistor using pulse width modulation. Preferably, the input impedance is controlled to be low for low signal levels and to be high for high signal levels, which results in a more reliable sensing of binary signals. The device may be used for detecting the state of contact transducers suffering from parasitic resistances caused by moist and/or polluted environments. Further, a method of sensing a binary signal is provided.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 2, 2014
    Assignee: ABB Technology AG
    Inventors: Hans Björklund, Krister Nyberg, Tommy Segerbäck
  • Publication number: 20140091833
    Abstract: A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Applicant: Infineon Technologies AG
    Inventors: David Astrom, Daniel Mandler
  • Publication number: 20140084958
    Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: SEMTECH CORPORATION
    Inventor: Daniel Kucharski
  • Patent number: 8680885
    Abstract: A low leakage logic circuit. The low leakage logic circuit includes a control circuit for logic circuit. The control circuit has a first transistor, a second transistor, a third transistor, a first diode, a first resistor and a second resistor. When the control circuit is ON, a first circuit path in the logic circuit is supplied with a first voltage from the source terminal of the third transistor. This voltage acts as a logic output and has the ability to source current at output terminal of the logic circuit. When the control circuit is OFF, a second circuit path in the logic circuit is supplied with a second voltage from the control circuit which is lower than the turn-on voltage of the second circuit path. This voltage is insufficient to turn ON the logic circuit, hence no current flows into the logic circuit.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Anadigics, Inc.
    Inventors: Valter Karavanic, Gary Hau
  • Publication number: 20140028346
    Abstract: A low supply voltage logic circuit includes a first current source operable to generate a first current dependent on a first control signal and to generate a first leakage current. A second current source is operable to generate a second current dependent on a second control signal and to generate a second leakage current. A third current source has a third current path between the output terminal and the first supply voltage terminal and is operable to generate a third current through the third current path to compensate for the second leakage current. A fourth current source has a fourth current path between the output terminal and the second supply voltage terminal and is operable to generate a fourth current through the fourth current path to compensate for the first leakage current.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Robert Kappel
  • Publication number: 20130328589
    Abstract: A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.
    Type: Application
    Filed: June 28, 2013
    Publication date: December 12, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Toshinao ISHII
  • Patent number: 8575956
    Abstract: A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate a first process signal, a first clock termination unit configured to be coupled with a first clock path and determine an impedance value responding to the impedance control signal, and a second clock termination unit configured to be coupled with a second clock path and determine an impedance value responding to the first process signal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: November 5, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Geun-Il Lee
  • Patent number: 8519736
    Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 27, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Arber Cauli, Luciano Prandi, Carlo Caminada
  • Patent number: 8497699
    Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 30, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Chang Ki Kwon, Greg A. Blodgett
  • Patent number: 8497700
    Abstract: Systems and methods pertaining to propagation of digital data from a transmit side domain to a receive side domain through an intermediate isolation barrier are described. Specifically, a carrier waveform is superimposed upon a first logic level of a digital signal that is referenced to a first local ground. The digital signal with the superimposed first carrier waveform is propagated through the intermediate isolation barrier. On the receive side domain, the propagated digital signal is processed using a second local ground that is different than the first local ground, the processing including the use of the carrier waveform to enforce the first logic level upon an output digital signal generated from the propagated digital signal.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 30, 2013
    Assignee: Samsung Electro-Mechanics
    Inventor: Geoffrey T Haigh
  • Patent number: 8421502
    Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Hon Shing Lau, Scott Siers, Ruchira Liyanage
  • Patent number: 8316336
    Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: David Overhauser
  • Patent number: 8305112
    Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: November 6, 2012
    Assignee: Intel Corporation
    Inventors: Hon Shing Lau, Scott Siers, Ruchira Liyanage
  • Patent number: 8294510
    Abstract: There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyoo Itoh, Masanao Yamaoka
  • Patent number: 8294487
    Abstract: The present invention provides an configuration setting device of integrated circuit and the configuration setting method thereof, in which the configuration setting device comprises a signal receiving terminal, a voltage output unit coupled to the signal receiving terminal, and a detector coupled to the signal receiving terminal. The signal receiving terminal is used to receive the input signal at the outer of the integrated circuit, and the voltage output unit generated at the inner of the integrated circuit is used to output a voltage signal based on the enable signal, and the detector is used to detect a level at the signal receiving terminal to output a configuration signal; wherein, the signal level generated at the signal receiving terminal is determined by the input signal and the voltage signal.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: October 23, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Meng-Han Hsieh, Chi-Shun Weng, Chien-Chih Chen
  • Patent number: 8289049
    Abstract: A signal level adjustment system adjusting a level of signal outputted from a signal output circuit is realized. An input buffer threshold adjustment unit sets a threshold of a signal input circuit to a first variable value. A signal level adjustment unit adjusts an output level of a first signal at the signal output circuit until a voltage of the first signal outputted from the signal output circuit and inputted to the signal input circuit falls into a given range determined based on the threshold.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 16, 2012
    Assignee: NEC Corporation
    Inventor: Yusuke Matsushima
  • Patent number: 8253440
    Abstract: Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: August 28, 2012
    Assignee: Intel Corporation
    Inventors: John Maddux, Luke A. Johnson, Ronald W. Swartz, Donald Rush, Meetul Goyal, Rajashri Doddamani
  • Publication number: 20120176152
    Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.
    Type: Application
    Filed: March 15, 2012
    Publication date: July 12, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Timothy M. Hollis
  • Patent number: 8212588
    Abstract: A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Theodore P. Haggis, Robert B. Likovich, Jr., James A. Mossman, Tiffany Tamaddoni-Jahromi, Robert B. Tremaine
  • Patent number: 8198917
    Abstract: The present invention provides a current segmentation circuit for optimizing output waveform from high speed data transmission interface, which comprises a four current sources controlled by four switches to segment current so as to control the rising and falling time of the high speed transmission data, and to match the delay of the current control signal and the delay of the data, wherein the four current sources are I1, I2, I3 and I4, and the current control switches are K1, K2, K3 and K4, wherein I1+I2=I3+I4, wherein the switches K1 and K3 control the current I1/I3 to flow into DP/DM line, and the switches K2 and K4 control the current I2/I4 to flow into DP/DM line. The present invention can depress overshoot and eliminate turning point in the waveform.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: June 12, 2012
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventors: Fei Ye, Xiangyang Guo, Guojun Zhu
  • Patent number: 8193828
    Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: June 5, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thierry Cassagnes, Valerie Bernon-Enjalbert, Philippe Lance, Matthijs Pardoen
  • Patent number: 8191033
    Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Marvell International Ltd.
    Inventor: Thomas Page Bruch
  • Patent number: 8164357
    Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: April 24, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Arber Cauli, Luciano Prandi, Carlo Caminada
  • Publication number: 20120068750
    Abstract: Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: Micron Technology, Inc.
    Inventor: John McCoy