Abstract: Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Some embodiments include a circuit having a logic circuit with an input stage and an output stage; a heterojunction bipolar transistor configured to provide a first switched supply voltage to power components of the input stage; and a depletion mode field effect transistor configured to provide a second switched supply voltage to power components of the output stage. Other embodiments may also be described and claimed.

Abstract: A sub-threshold voltage circuit of multi-channel length includes a plurality of logic gates, which are electrically connected with one another according to a predetermined manner and composed of a plurality of PMOS transistors and a plurality of NMOS transistors. The logic gates form a plurality of signal paths defining at least one key signal path and a plurality of general signal paths respectively. The channel lengths of the logic gates located on the general signal paths each are the minimum channel length of the manufacturing process of the transistor. The logic gate located on the at least one key signal path is an RSCE PMOS or NMOS transistor, the channel length of which is larger than the minimum channel length of the manufacturing process of the transistor to define a maximum channel length. Thus, the performance is enhanced, leakage current is less, and the circuit area keeps proper in degree.

Abstract: A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.

Abstract: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state.

Abstract: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed.

Abstract: An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal.

Abstract: A circuit for restraining a shoot through current comprises a master selecting unit and a logic unit. The master selecting unit receives an input signal, and outputs first and second master selecting signals. The logic unit comprises first and second logic elements which generate first and second control signals for controlling two transistor switches connected in series. The first and second logic elements change the logic states of the first and second control signals according to the first and second master selecting signals. When the input signal is at a first logic level, the first logic element acquires a control privilege to change the logic state of the first control signal and trigger the second logic element to change the logic state of the second control signal. When the input signal is at a second logic, the second logic element acquires the control privilege.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: A semiconductor buffer circuit that operates stably against PVT fluctuation is disclosed. The disclosed semiconductor buffer unit of the present invention includes: a detecting block configured to generate a plurality of code signals by detecting an external voltage, using a plurality of reference voltages; and a buffer unit configured to receive an input signal and the plurality of code signals and, based on the code signals, to generate an output signal, wherein a consumption of a driving current of the buffer unit is controlled based on the code signals.

Abstract: An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

Abstract: A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage.

Abstract: A data output circuit includes a plurality of drivers configured to be turned on/off according to impedance codes to output data to an output node. The impedance codes are divided into a first group having a value to turn on the drivers, and a second group having a value to turn off the drivers, and at least some of the drivers controlled by the second group are turned on during a pre-emphasis period.

Abstract: The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: A transistor gate driving circuit is developed for power saving. It includes a first high-side transistor, a second high-side transistor and a low-side transistor. A voltage clamp device is connected to the gate terminal of the first high-side transistor to limit the maximum output voltage. A detection circuit is coupled to detect a feedback signal of the power converter. The feedback signal is correlated to the output load of the power converter. The detection circuit will generate a disable signal in response to the level of the feedback signal. The disable signal is coupled to disable the second high-side transistor once the level of the feedback signal is lower than a threshold.

Abstract: The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A termination resistance adjusting circuit includes a first termination resistor circuit, a second termination resistor circuit connected in parallel with the first termination resistor circuit, a resistor circuit for adjustment that adjusts resistances of the first and second termination resistor circuits, a first amplifier circuit that receives a first voltage determined by the resistor circuit for adjustment and a second voltage determined by a reference resistor connected externally, equalizes the first and second voltages, and outputs a resistance adjusting signal to the first and second termination resistor circuits, first and second terminals connected to the first and second termination resistor circuits respectively, and a second amplifier circuit that receives a voltage based on a common voltage of a differential signal supplied to the first and second terminals, and the first or second voltage, and equalizes the voltage based on the common voltage and the first or second voltage.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wher

Abstract: The separate high speed and full speed drivers used in a Universal Serial Bus 2.0 application can be combined into one driver which functions both as full speed/high speed driver and as a result provides output impedance for the full speed/high speed modes which is less process dependent.

Abstract: Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The absence of an explicit near-end driver termination improves efficiency, while replica biasing controls output voltage swing levels. Hot-pluggable compatibility is achieved by a reduction in power-off leakage current and short circuit current protection.

Abstract: A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

Abstract: A semiconductor integrated circuit device comprises a transistor circuit exhibiting inductance at a desired frequency owing to capacitance between electrodes in a MOS transistor, the transistor circuit having an impedance that increases with an increase in frequency; and a first MOS transistor that functions as a source follower having the transistor circuit as a load.

Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.

Abstract: There is provided a current amount adjusting section adjusting a current amount flowing through a power supply line supplying power to an internal circuit which includes a circuit operating based on a clock signal and a ratio of consumed charge amounts by the current flowing at a rising edge of the clock signal and by the current flowing at a falling edge of the clock signal so that noise generated in the power supply line may be restrained.

Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage.

Abstract: In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.

Abstract: A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a first power line maintained at a low-level source voltage; a second circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a second power line maintained at a low-level source voltage; a power line switch section connected between the first and second power lines; and a control circuit adapted to control the power line switch section so that the first and second power lines are connected together at a later timing or gradually over a longer period of time than the switching transistor turns on.

Abstract: An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conducted through a transistor connected in series with a variable value resistance in the integrated circuit at the circuit node. A resistance value of the variable value resistance is varied to establish a value of the calibration current which establishes the desired output impedance. The calibration mode is exited and a functional mode is entered. A calibrated resistance value is used during the functional mode of operation. The calibration current is conducted as a calibrated current through the transistor and calibrated resistance value. Variation of the calibrated current is corrected in response to voltage and process variations to maintain the calibrated current and output impedance of the driver circuit.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.