With Flip-flop Or Sequential Device Patents (Class 326/40)
  • Patent number: 10409615
    Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 10, 2019
    Assignee: The Regents of the University of Michigan
    Inventors: Yajing Chen, Trevor Mudge, Ronald Dreslinski, Jr., Shengshuo Lu, Hun Seok Kim, David Theodore Blaauw, Fu Cheng
  • Patent number: 10320389
    Abstract: Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 11, 2019
    Assignee: Synopsys, Inc.
    Inventors: Vijay A. Nebhrajani, Sanket Naik
  • Patent number: 10235185
    Abstract: A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 19, 2019
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Ying-Xian Han
  • Patent number: 10224908
    Abstract: An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used to compute first calibration settings that take into account jitter and process variations. The monitoring circuit may be used to measure a proxy parameter of interest. The processing circuit may be used to compute an offset based at least partly on the measured value of the proxy parameter. The offset may be applied to the first calibration settings to obtain second calibration settings, which can be used to configure the respective delay paths.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventors: Joshua David Fender, Navid Azizi, Gordon Raymond Chiu
  • Patent number: 10224907
    Abstract: A control module for a generator exercise timer enables a user to conduct generator exercise sessions at intervals longer than predetermined intervals permitted by the manufacturer. The control module can be connected in series with a generator's existing electronic exerciser timer, preferably by disconnecting the existing exerciser timer's wiring harness from the exercise timer and connecting the control module to the exercise timer. The control module can be provided with a connector of its own to which the wiring harness can be connected. The control module includes a latching relay and a non-latching relay that can be operated in such a manner that alternating “engine start” signals are sent to the generator. Thus, the exercise timer will be effective to exercise the generator at delayed intervals, e.g., every other week rather than every week. The control module includes a pushbutton switch and a visible LED.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 5, 2019
    Inventor: Gary D. Redpath
  • Patent number: 10122364
    Abstract: Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: November 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 10103963
    Abstract: A network appliance described herein allows the user to selectively forward the flow of packets received through a network port, to a particular egress port. The network appliance creates virtual ports, which can be assigned to the one or more egress ports. The network appliance assigns the flow of packets to the one or more virtual ports in the network appliance. The network appliance decides a forwarding treatment to be applied to the flow of packets, for forwarding the flow of packets to the egress tool ports, based on the virtual port to which the flow of packets is assigned and based on a detected network characteristic. The forwarding treatment can be a decision to drop the flow of packets, or to send the flow of packets to the egress port assigned to the virtual port.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 16, 2018
    Assignee: Gigamon Inc.
    Inventors: Ayyappa Nuthalapati, Bhanu Prathap Reddy Parlapalli, Andrew Mao, Qi Ming Ng
  • Patent number: 10084455
    Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: September 25, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Patent number: 10073115
    Abstract: A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) may be capable of real time or near-real time diagnostic processing to determine potential accelerometer issues during flight or other mission critical operational situations. The SDA FPGA may determine accelerometer structural health and an attachment condition using an electronics system that is smaller, more energy efficient, and more cost effective than previous diagnostic tools. Advantages of the system may include diagnosing sensors automatically, immediately, actively (i.e., confirming the fault), and consistently, without the influence of a human operator. Customizable SDA algorithms may be adjusted to the specific needs of the sensor/environment.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 11, 2018
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventors: Roger P. Tokars, John D. Lekki
  • Patent number: 10037793
    Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 31, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jeong-Tae Hwang
  • Patent number: 10020811
    Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 10, 2018
    Assignee: Microsemi SoC Corp.
    Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
  • Patent number: 9793080
    Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 17, 2017
    Assignee: INOSO, LLC
    Inventors: Kiyoshi Mori, Ziep Tran, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 9768784
    Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration bits, a second multiplexer stage, and means for connecting either outputs of the first multiplexer stage or the output of the second multiplexer stage to corresponding logic circuits. The vectored multiplexing circuits may be used to generate multiple signal variants to vectored lookup table circuitry. The vectored lookup table circuitry may include a first stage of LUTs sharing some number of inputs and a second stage of LUTs at least some of which can be switched out of use. The second stage of LUTs may have inputs that are deactivated in a fractured mode.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 19, 2017
    Assignee: Altera Corporation
    Inventor: John Curtis Van Dyken
  • Patent number: 9645635
    Abstract: A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One advantage of the disclosed technique is that sleep FET usage is reduced, thereby countering the effects of FET deterioration due to BTI and TDDB. Accordingly, the lifetime of sleep FETs configured to perform power gating for logic blocks may be extended.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: May 9, 2017
    Assignee: NVIDIA Corporation
    Inventors: Sachin Idgunji, Tezaswi Raja
  • Patent number: 9626325
    Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 18, 2017
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Patent number: 9600414
    Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 21, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Luca Porzio, Rodolphe Sequeira
  • Patent number: 9489300
    Abstract: A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to increase average reliability by reducing an average number of state changes of storage elements per write operation and to reduce average write time by reducing a number of operations for storing the mapped value into the storage elements.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 8, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Menahem Lasser
  • Patent number: 9395413
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 19, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Patent number: 9356604
    Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Thomas Nirschl, Gerd Dirscherl, Philip Schlazer, Stefan Rueping
  • Patent number: 9348792
    Abstract: A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moo-Kyoung Chung, Yeon-Gon Cho, Soo-Jung Ryu
  • Patent number: 9337843
    Abstract: Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 9300298
    Abstract: A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Robert B. Tremaine
  • Patent number: 9285426
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Patent number: 9231595
    Abstract: A method for efficient logging in a control system is provided. A first plurality of registers, frequently accessed registers, is identified. A request is received from a server to access at least one of the first plurality of registers. The request includes a second plurality of registers and a plurality of data values to be stored in the second plurality of registers. At least some registers included in the request are frequently accessed registers. A third plurality of registers is identified based on predetermined criteria for inclusion. The third plurality of registers is a subset of the second plurality of registers storing a corresponding subset of the plurality of data values. A log entry is stored in an event log file corresponding to each data value included the third plurality of registers.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventor: Enrique Q. Garcia
  • Patent number: 9208858
    Abstract: A static random access memory (SRAM) includes a first port word line, a second port word line, a first port bit line and a first port complementary bit line, a second port bit line and second port complementary bit line, and a memory cell having a data node coupled to the first and second port bit lines and a complementary data node coupled to the first and second port complementary bit lines. The first and second port word lines control access to the dual port memory cell. A circuit couples the second port bit line to a high voltage supply node during a write logic high operation to the data node through the first port bit line and couple the second port complementary bit line to the high voltage supply node during a write logic high operation to the complementary data node through the first port complementary bit line.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kao-Cheng Lin, Hidehiro Fujiwara, Wei Min Chan, Yen-Huei Chen
  • Patent number: 9189199
    Abstract: Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 17, 2015
    Assignee: NVIDIA Corporation
    Inventor: Robert A. Alfieri
  • Patent number: 9165942
    Abstract: An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 9157958
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 13, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Patent number: 9143122
    Abstract: A system includes: an initial clock region; a first adjacent clock region adjacent to the initial clock region; a spine coupled to receive a clock signal from a clock; and a first phase detector coupled to detect a difference in phase between the initial clock region and the first adjacent clock region. The initial clock region comprises an initial delay element coupled to the spine and to the first phase detector.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: September 22, 2015
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 9134750
    Abstract: An embedded multimedia card (eMMC) communicating with a host includes; a latch circuit that receives and latches a data signal according to either a first edge or a second edge of a clock to thereby generate a latched data signal, and a start bit detector that detects in the latched data signal a start bit and provides a valid data signal from a portion of the latched data signal following the start bit.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Gyu Kang, Sung Ho Seo, Myung Sub Shin, Kyung Phil Yoo, Jung Pil Lee, Jun Ho Choi
  • Patent number: 9117501
    Abstract: To optimize the arrangement of configuration data stored in a configuration memory. A lookup table includes a memory configured to store configuration data, a plurality of multiplexers each configured to select one signal from a plurality of input signals in accordance with the configuration data supplied from the memory and output the one signal, and an inverter. The plurality of multiplexers are connected in a binary tree with multiple levels. The inverter is provided between one of input terminals of a multiplexer in an uppermost level and an output terminal of a multiplexer in one level lower than the uppermost level. Signal selection is performed in each of the multiplexers so that the multiplexer in the uppermost level outputs, as an output signal, one signal of all input signals of the multiplexers in a lowermost level.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 25, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9112499
    Abstract: Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 18, 2015
    Assignee: Unity Semiconductor Corporation
    Inventor: Robert Norman
  • Patent number: 9087615
    Abstract: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Timothy J. Dell, Anil B. Lingambudi, Diyanesh B. Vidyapoornachary
  • Patent number: 9071246
    Abstract: A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 30, 2015
    Assignee: Agate Logic, Inc.
    Inventors: Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Jason Golbus, Dana L. How
  • Patent number: 9063197
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 23, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Patent number: 9048833
    Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 2, 2015
    Assignee: TABULA, INC.
    Inventor: Jason Redgrave
  • Patent number: 9018977
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 28, 2015
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Herman Schmit
  • Patent number: 9018975
    Abstract: Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Intel Corporation
    Inventors: Nicholas P. Cowley, Ramnarayanan Muthukaruppan
  • Patent number: 9018978
    Abstract: A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 28, 2015
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Patent number: 9013208
    Abstract: Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit includes a multiplexer and a logic module coupled to the multiplexer. The multiplexer is configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. The logic module includes at least one of an XNOR and an XOR module and is configured to provide an output signal that is responsive to performing at least one of an XNOR and an XOR operation of the output of the multiplexer and an enable signal that enables or disables the clock gate circuit to generate the clock signal.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 21, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Eitan Rosen
  • Patent number: 9007089
    Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: April 14, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Tung-Cheng Kuo, Sheng-Kai Chen
  • Patent number: 8996906
    Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 31, 2015
    Assignee: Tabula, Inc.
    Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
  • Patent number: 8981813
    Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: March 17, 2015
    Assignee: Agate Logic, Inc.
    Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
  • Patent number: 8975918
    Abstract: To optimize the arrangement of configuration data stored in a configuration memory. A lookup table includes a memory configured to store configuration data, a plurality of multiplexers each configured to select one signal from a plurality of input signals in accordance with the configuration data supplied from the memory and output the one signal, and an inverter. The plurality of multiplexers are connected in a binary tree with multiple levels. The inverter is provided between one of input terminals of a multiplexer in an uppermost level and an output terminal of a multiplexer in one level lower than the uppermost level. Signal selection is performed in each of the multiplexers so that the multiplexer in the uppermost level outputs, as an output signal, one signal of all input signals of the multiplexers in a lowermost level.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8963581
    Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah, David Galloway, Tim Vanderhoek
  • Patent number: 8952721
    Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 10, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Takashi Ishiguro, Masayuki Sato, Tetsuo Hironaka, Hitoshi Shimazaki
  • Patent number: 8952720
    Abstract: A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Oda, Shinichi Yasuda, Koichiro Zaitsu
  • Patent number: 8952722
    Abstract: Configuration is performed in accordance with a plurality of states when power supply voltage is supplied intermittently. At the time of start of supply of power supply voltage with configuration, a programmable logic device is sequentially changed into a first state where configuration data is not set in a configuration memory, a second state where the configuration memory is initialized, and a third state where the configuration data can be set in the configuration memory. At the time of start of supply of power supply voltage without configuration, the programmable logic device is sequentially changed into a fourth state where the configuration data is not set in the configuration memory and the third state. The first to fourth states are switched to any one of the states by control of a first state signal and a second state signal.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 8952723
    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 8941409
    Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Tabula, Inc.
    Inventors: Martin Voogel, Steven Teig, Trevis Chandler