Abstract: A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: In general, the present invention relates to a virtual platform in which one or more distributed virtual switches can be created for use in virtual networking. According to some aspects, the distributed virtual switch according to the invention provides the ability for virtual and physical machines to more readily, securely, and efficiently communicate with each other even if they are not located on the same physical host and/or in the same subnet or VLAN. According other aspects, the distributed virtual switches of the invention can support integration with traditional IP networks and support sophisticated IP technologies including NAT functionality, stateful firewalling, and notifying the IP network of workload migration. According to further aspects, the virtual platform of the invention creates one or more distributed virtual switches which may be allocated to a tenant, application, or other entity requiring isolation and/or independent configuration state.

Abstract: A processor has first, second and third ALUs. The first ALU has on a first side an input and an output. The second ALU has a first side facing the first side of the first ALU, an input and an output on the first side of the second ALU and being in a rotated orientation relative to the input and the output of the first side of the first ALU, and an output on a second side of the second ALU. The third ALU has a first side facing the second side of the second ALU, and an input and an output on the first side of the third ALU. The input of the first side of the first ALU is logically directly connected to the output of the first side of the second ALU.

Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A system and method for updating storage system includes a solid state disk (SSD) attached to a FPGA. The solid state disk is configured to receive a firmware image and a firmware upgrade module operating on the FPGA is configured to identify the presence of the firmware image on the SSD. The firmware upgrade module is further configured to store the firmware image in a buffer on the FPGA and write the firmware image.

Abstract: Provided are a latch and a drive method thereof, a source drive circuit and a display device. The latch includes: a first latch circuit and a second latch circuit; the first latch circuit is connected to a first control signal terminal, a data signal terminal and a transmission node, and is configured to latch a data signal from the data signal terminal at a first latch node and transmit the data signal to the transmission node; and the second latch circuit is connected to the transmission node, a first switch signal terminal, a second switch signal terminal and an output node, and is configured to latch a data signal from the transmission node at a second latch node and output the data signal to the output node; a loop in the second latch circuit is turned off in response to the data signal written to the second latch node.

Abstract: The present disclosure provides circuits and methods that can be used to update configurations. An example circuit can include a plurality hLUTs and a plurality of registers configured to propagate a set of data or a portion thereof to the plurality of hLUTs. An hLUT of the plurality of hLUTs can have a transformation unit comprising transformation circuitry configured to (i) receive the set of data or the portion thereof from a register of the plurality of registers and (ii) transform the set of data or the portion thereof into configurations for the hLUT.

Abstract: Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

Abstract: An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.

Abstract: A circuit comprises a clock gating device. The clock gating device comprises a multiplexing device and circuitry for generating multiplexer input signals. The selector input of the multiplexing device is coupled to a clock signal. The multiplexing device selects the first input signal to send to an output of the multiplexing device when the selector input is set to “0” and selects the second input signal to send to the output of the multiplexing device outputted when the selector input is set to “1”. The circuitry for generating multiplexer input signals is configured to ensure the timing of the transitions on the output are derived from the timing of the transitions of the clock signal and not by the timing of the transition of the first and second inputs of the multiplexing device.

Abstract: A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partial products can be calculated first sequentially across the set of rows and second sequentially across the bit positions of the elements of the second matrix. Alternatively, the partial products can be calculated first sequentially across the bit positions of the elements of the second matrix first and second sequentially across the set of rows. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Abstract: Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Abstract: A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Abstract: A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.

Abstract: The present disclosure relates to a computer-implemented method for performing a reset sequence simulation in an electronic design. The method may include receiving, using at least one processor, a sequence file including at least one reset, input and cycle value. The method may further include sampling during a first set of cycles set forth in the sequence file and detecting stability at a time point during a first set of cycles. The method may also include bypassing sampling during one or more remaining time points of the first set of cycles, sampling during a second set of cycles set forth in the sequence file and detecting stability at a time point during a second set of cycles.

Abstract: A power distribution assembly according to an example of the present disclosure includes, among other things, a housing at least partially receiving a plurality of hardware modules coupled to a backplane, the plurality of hardware modules including at least one output module and a communications module that communicates information between the plurality of hardware modules and a second power distribution assembly. At least one hardware module of the plurality of hardware modules includes a field programmable gate array that commands the at least one output module to selectively power at least one aircraft system. A method of operation of a power distribution system is also disclosed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to capture two or more concurrent images of a scene with two or more cameras, detect a feature in a first image from a first camera of the two or more cameras, match the feature in a second image from a second camera of the two or more cameras, and perform a photometric calibration between the first camera and the second camera based on a portion of the first image corresponding to the detected feature and a portion of the second image corresponding to the matched feature. Other embodiments are disclosed and claimed.

Abstract: Example communication systems and methods are described. In one implementation, a method receives a first chaotic sequence of a first temporal length, and a second chaotic sequence of a second temporal length. The method also receives a data symbol for communication to a destination. Based on the data symbol, the second chaotic sequence is temporally shifted and combined with the first chaotic sequence to generate a composite chaotic sequence. The first chaotic sequence functions as a reference chaotic sequence while the second chaotic sequence functions as a data-carrying auxiliary chaotic sequence.

Abstract: A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Abstract: A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

Abstract: A field-programmable operation array includes an interconnect network and a plurality of operation blocks, including a first operation block and a second operation block, electrically connected to the interconnect network. Each operation block includes an arithmetic logic unit and a plurality of logic gates. A pass signal output by the arithmetic logic unit of the first operation is received by the arithmetic logic unit of the second operation block.

Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.

Abstract: Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

Abstract: A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.

Abstract: A control module for a generator exercise timer enables a user to conduct generator exercise sessions at intervals longer than predetermined intervals permitted by the manufacturer. The control module can be connected in series with a generator's existing electronic exerciser timer, preferably by disconnecting the existing exerciser timer's wiring harness from the exercise timer and connecting the control module to the exercise timer. The control module can be provided with a connector of its own to which the wiring harness can be connected. The control module includes a latching relay and a non-latching relay that can be operated in such a manner that alternating “engine start” signals are sent to the generator. Thus, the exercise timer will be effective to exercise the generator at delayed intervals, e.g., every other week rather than every week. The control module includes a pushbutton switch and a visible LED.

Abstract: An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used to compute first calibration settings that take into account jitter and process variations. The monitoring circuit may be used to measure a proxy parameter of interest. The processing circuit may be used to compute an offset based at least partly on the measured value of the proxy parameter. The offset may be applied to the first calibration settings to obtain second calibration settings, which can be used to configure the respective delay paths.

Abstract: Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.

Abstract: A network appliance described herein allows the user to selectively forward the flow of packets received through a network port, to a particular egress port. The network appliance creates virtual ports, which can be assigned to the one or more egress ports. The network appliance assigns the flow of packets to the one or more virtual ports in the network appliance. The network appliance decides a forwarding treatment to be applied to the flow of packets, for forwarding the flow of packets to the egress tool ports, based on the virtual port to which the flow of packets is assigned and based on a detected network characteristic. The forwarding treatment can be a decision to drop the flow of packets, or to send the flow of packets to the egress port assigned to the virtual port.

Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Abstract: A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) may be capable of real time or near-real time diagnostic processing to determine potential accelerometer issues during flight or other mission critical operational situations. The SDA FPGA may determine accelerometer structural health and an attachment condition using an electronics system that is smaller, more energy efficient, and more cost effective than previous diagnostic tools. Advantages of the system may include diagnosing sensors automatically, immediately, actively (i.e., confirming the fault), and consistently, without the influence of a human operator. Customizable SDA algorithms may be adjusted to the specific needs of the sensor/environment.

Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration bits, a second multiplexer stage, and means for connecting either outputs of the first multiplexer stage or the output of the second multiplexer stage to corresponding logic circuits. The vectored multiplexing circuits may be used to generate multiple signal variants to vectored lookup table circuitry. The vectored lookup table circuitry may include a first stage of LUTs sharing some number of inputs and a second stage of LUTs at least some of which can be switched out of use. The second stage of LUTs may have inputs that are deactivated in a fractured mode.

Abstract: A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One advantage of the disclosed technique is that sleep FET usage is reduced, thereby countering the effects of FET deterioration due to BTI and TDDB. Accordingly, the lifetime of sleep FETs configured to perform power gating for logic blocks may be extended.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.

Abstract: A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to increase average reliability by reducing an average number of state changes of storage elements per write operation and to reduce average write time by reducing a number of operations for storing the mapped value into the storage elements.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract: A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.

Abstract: Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.

Abstract: A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.