Array (e.g., Pla, Pal, Pld, Etc.) Patents (Class 326/39)
  • Patent number: 11188497
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 30, 2021
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Patent number: 11183246
    Abstract: A memory device includes a first plane defined in a second wafer stacked on a first wafer; a second plane defined in a third wafer stacked on the second wafer, and overlapping with the first plane in a vertical direction; a first page buffer circuit including a first column driver coupled to bit lines of the first plane and a first column operator; and a second page buffer circuit including a second column driver coupled to bit lines of the second plane and a second column operator. The first column driver is disposed in the second wafer, the second column driver is disposed in the third wafer and overlaps with the first column driver in the vertical direction, and the first and second column operators are disposed in a cell region of the first wafer and overlap with the first and second planes in the vertical direction.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Won Seok Kim, Sang Woo Park
  • Patent number: 11171652
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 9, 2021
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 11159453
    Abstract: By querying a set of fabrics to determine an initiator logged into a fabric in the set of fabrics, a set of accessible fabrics is discovered, an accessible fabric in the set of accessible fabrics accessible to the initiator, an initiator comprising a transceiver connecting a server to a switch, a fabric in the set of fabrics comprising a switch connecting a server to a storage device, the storage device comprising a storage volume. Using a fabric usage policy, a set of allowed fabrics within the set of accessible fabrics is determined. Using the set of allowed fabrics, a storage volume is mapped to a server, the mapping enabling the server to access the storage volume via a fabric in the set of allowed fabrics.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gerald Francis McBrearty
  • Patent number: 11144652
    Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ellery Cochell, Brian S. Martin, Ravi N. Kurlagunda
  • Patent number: 11121021
    Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: September 14, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman
  • Patent number: 11106616
    Abstract: Examples described herein generally relate to a Peripheral Connect Interconnect Express (PCIe) device. An example is a non-transitory memory storing a representation of a design that is to be implemented on a programmable integrated circuit. The design includes a classifier module (CM), a message trap engine module (MTEM), and a configuration space. The CM is capable of receiving a PCIe message and is configured to determine whether the PCIe message is a PCIe Type 1 configuration transaction. The CM is configured to forward the PCIe message to an endpoint device and to the MTEM when the PCIe message is a non-PCIe Type 1 configuration transaction and the PCIe Type 1 configuration transaction, respectively. The MTEM is configured to virtualize a downstream port(s) of a virtual switch and maintain the configuration space. The MTEM is capable of accessing the configuration space in response to the PCIe message.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 31, 2021
    Assignee: XILINX, INC.
    Inventor: Chunhua Wu
  • Patent number: 11101801
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 24, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11088693
    Abstract: A method for mapping a Boolean function to a configurable logic block (CLB). The CLB includes a first plurality of programmable logic cells (PLCs). The Boolean function includes a plurality of digits. Each of the plurality of digits includes a respective hexadecimal value. The method includes mapping the Boolean function to a first PLC of the first plurality of PLCs responsive to the plurality of digits satisfying a first condition. In an exemplary embodiment, the first condition includes at least two digits of the plurality of digits being different and each of the plurality of digits including one of a first hexadecimal digit, a second hexadecimal digit different from the first hexadecimal digit, a bitwise complement of the first hexadecimal digit, and a bitwise complement of the second hexadecimal digit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 10, 2021
    Inventors: Hossein Asadi, Elmira Nezamfar, Zeinab Seifoori
  • Patent number: 11080048
    Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Jesus Corbal, Dan Baum, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil, Raanan Sade
  • Patent number: 11073484
    Abstract: An image acceleration processing device including a field programmable gate array (FPGA) processing platform; and a personal computer (PC). The FPGA processing platform includes: a first fiber interface configured to receive configuration parameters and test commands, and to output test results; a second fiber interface configured to exchange data with the PC; a third fiber interface configured to receive image data and output the configuration parameters and the test commands; a fourth fiber interface configured to control the generation of a screen lighting signal; and a fifth fiber interface configured to control an input/output (IO) light source.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 27, 2021
    Assignee: WUHAN JINGCE ELECTRONIC GROUP CO., LTD.
    Inventors: Changdong Ou, Zhou Wang, Biaohua Deng, Wentian Tang, Linhai Mei, Wenzhong Dong, Bo Li, Moxiao Xu
  • Patent number: 11074970
    Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
  • Patent number: 11061853
    Abstract: A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 13, 2021
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks, Douglas R. Reed
  • Patent number: 11018191
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include replacement gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 10990547
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Patent number: 10990737
    Abstract: A secure one-way network gateway for transmitting data from a source network to a destination network is disclosed. An input circuit is for coupling to a source network and an output circuit is for coupling to an output network. A memory stores configuration data. Either a single field-programmable device or a pair of field-programmable devices coupled via a one-way link are inserted between the input circuit and the output circuit. The configuration data is loaded into the device(s) to program the device(s) to pass data from the input circuit to the output circuit, to optionally filter the data, and to prevent any data from passing from the output circuit to the input circuit. A processor is coupled to only the memory and a separate management interface. The processor receives updated configuration data via the management interface and replaces the configuration data in the memory with the updated configuration memory.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 27, 2021
    Assignee: Owl Cyber Defense Solutions, LLC
    Inventors: Steven Staubly, Michael T. Tsao, Brian Kane
  • Patent number: 10963306
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 30, 2021
    Assignee: ThroughPuter, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 10949204
    Abstract: A microcontroller has a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell. The configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal. The central processing unit is configured to directly provide input address signals for the look-up table.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Ryan Foss
  • Patent number: 10936221
    Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, James Brian Johnson
  • Patent number: 10886922
    Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10884476
    Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Vinu K. Elias, Sundar Ramani, Arvind S. Tomar, Jianjun Liu
  • Patent number: 10886923
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 5, 2021
    Assignee: Google LLC
    Inventor: Jonathan Ross
  • Patent number: 10879903
    Abstract: An integrated circuit device is disclosed that includes an interposer and a programmable fabric die disposed on the interposer. The programmable fabric die includes multiple sectors that each have multiple rows of logic element blocks. Each row of logic element blocks includes multiple microbumps. Each logic element block has programmable fabric circuitry and an input/output interface electrically coupled to a respective microbump. The integrated circuit device also includes a device disposed on the interposer external to the programmable fabric die and electrically coupled to the microbumps via the interposer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey Chromczak, Paul Rotker
  • Patent number: 10879904
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 29, 2020
    Assignee: X Development LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 10866376
    Abstract: A method and system of co-packaging optoelectronics components or photonic integrated circuit (PIC) with application specific integrated circuits (ASICs) are disclosed and may include package substrate, several electronics die, passive components, socket assembly, and heat sinks. The said method converts ASIC high speed signals to optical signals by eliminating intermediary electrical interface between the ASIC and conventional optical modules. The method described provides many advantages of pluggable optical modules such as configurability, serviceability, and thermal isolation from the ASIC heat, while eliminating bandwidth bottlenecks as result of the ASIC package, host or linecard printed circuit board (PCB) traces, and the optical module connector. The high-power consumption ASIC is mounted below the package substrate, but sensitive optoelectronics and PIC components are mounted on top of the package substrate assembly for thermal isolation and serviceability.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 15, 2020
    Inventor: Ali Ghiasi
  • Patent number: 10860253
    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Thomas Vogelsang
  • Patent number: 10852800
    Abstract: A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Duc Dang, Ty Doan, Pinchas Herman, Zhanhe Shi
  • Patent number: 10855285
    Abstract: Illustrative embodiments provide a field-programmable transistor array and a method of making an integrated circuit comprising a field-programmable transistor array. The field-programmable transistor array comprises a plurality of logic cells. Each of the plurality of logic cells comprises a plurality of columns of transistors. Each of the plurality of columns of transistors comprises a plurality of first transistors and a plurality of second transistors. Each of the plurality of first transistors are individually programmable to be either always on, always off, or to be controlled by a logic signal to be on or off. Each of the plurality of second transistors are configured to be programmed to be always on or always off.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Carl Sechen, Georgios Makris, Gaurav Rajavendra Reddy, Jingxiang Tian
  • Patent number: 10855278
    Abstract: Modular layout design units are provided with an internal channel for multi-directional distribution of a shared signal. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each modular unit having an internal channel for signal distribution. The internal channel possesses: an edge connection on each edge of the modular unit; a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer with at least one of the incoming and outgoing buffers disabled, the bi-directional buffers cooperating to steer a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap providing the signal for use by internal circuitry of the modular unit.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 1, 2020
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Joe Sheredy, Lawrence Chi Fung Cheng
  • Patent number: 10838876
    Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10797702
    Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 6, 2020
    Assignee: Altera Corporation
    Inventor: Tony K. Ngai
  • Patent number: 10790830
    Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton
  • Patent number: 10789000
    Abstract: Provided is a variable electronic apparatus including a memory unit, a processing unit and a programmable logic gate device. The memory unit stores configuration data. The processing unit reads the configuration data from the memory unit and determines at least one control mode based on the configuration data. The programmable logic gate device includes a plurality of function modules and at least one switching unit. When the control mode includes a function module selecting mode and a signal line switching mode, the processing unit selects or activates the function modules of the programmable logic gate device based on the function module selecting mode, and the switching unit of the programmable logic gate device dynamically modifies or adaptably adjusts a bus of the function module selected by the processing unit and a corresponding external signal line based on the signal line switching mode.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 29, 2020
    Assignee: AEWN TECHNOLOGIES CO., LTD.
    Inventor: Ming-Lun Shao
  • Patent number: 10776183
    Abstract: An information processing apparatus includes, a programmable circuit that includes multiple areas into which logics are capable of being programmed, a memory, and a processor configured to, receive a request including information concerning a first process and a second process, calculate a first throughput corresponding to the first process and a second throughput corresponding to the second process based on data used in each of the first process and the second process, determine a first number of areas in which the first process is performed and a second number of areas in which the second process is performed, and program first logics to perform the first process in first areas among the multiple areas, and program second logics to perform the second process in second areas among the multiple areas, the first areas corresponding to the first number, the second areas corresponding to the second number.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hidetoshi Matsumura, Yasuhiro Watanabe
  • Patent number: 10754793
    Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10754993
    Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 25, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Kenneth R. Weidele, Kenneth F. McKinney, Christopher H. Meawad, Tim Manestitaya, Allan T. Hilchie, Timothy D. Schaffner
  • Patent number: 10726181
    Abstract: A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 28, 2020
    Assignee: XILINX, INC.
    Inventors: Martin L. Voogel, Trevor J. Bauer, Henri Fraisse
  • Patent number: 10725102
    Abstract: An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Semitronix Corporation
    Inventor: Fan Lan
  • Patent number: 10720927
    Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 21, 2020
    Assignee: Altera Corporation
    Inventor: Laura Reese
  • Patent number: 10715144
    Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Sergey Gribok, Gregg Baeckler, Martin Langhammer
  • Patent number: 10706898
    Abstract: A semiconductor apparatus may include: a pad unit including a plurality of pads; a memory cell array coupled to the pad unit through input/output signal lines; and a pad configuration control circuit configured to change a pad configuration of the pad unit by dividing the plurality of pads into a plurality of groups and setting the plurality of groups to different modes, respectively.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Myoung Seo Kim, Seung Yong Lee, Young Pyo Joo
  • Patent number: 10691634
    Abstract: Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 23, 2020
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10691860
    Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 23, 2020
    Assignee: RAMBUS INC.
    Inventors: Lap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
  • Patent number: 10686448
    Abstract: An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 16, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
  • Patent number: 10680616
    Abstract: An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Geoffrey R. Tate, Cheng C. Wang
  • Patent number: 10671148
    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 2, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
  • Patent number: 10637478
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 28, 2020
    Inventor: Jonathan Ross
  • Patent number: 10620998
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 14, 2020
    Assignee: ThroughPuter, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 10608638
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 31, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10600772
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa