Array (e.g., Pla, Pal, Pld, Etc.) Patents (Class 326/39)
  • Patent number: 11870694
    Abstract: A CPE receives, over a first connection with a wireless network, a network-assigned prefix for the CPE. The CPE creates a prefix based on a subset of bits from the network assigned prefix. The CPE transmits, over a second connection with a LAN router device, the prefix created by the CPE as a WAN prefix for the LAN router device and the network assigned prefix as a LAN prefix for the LAN router device.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 9, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Prathamesh Prakash Prabhudesai, Gaurav Gopal Kathuria, Rohit Tripathi, Reddy Surendra Prasad Bangalore Venkataswamy
  • Patent number: 11869847
    Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11843377
    Abstract: A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 12, 2023
    Assignee: Gowin Semiconductor Corporation
    Inventor: Jinghui Zhu
  • Patent number: 11803508
    Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: October 31, 2023
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Ananth Durbha, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11789610
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • Patent number: 11742001
    Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Arm Limited
    Inventors: Fakhruddin Ali Bohra, Lalit Gupta, Shri Sagar Dwivedi
  • Patent number: 11726745
    Abstract: A product-sum operation device, a neuromorphic device, and a method for using the product-sum operation device are provided which can, when applied to a neural network, curb the possibility that the performance of the neural network may be greatly impaired. The product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of product operation elements, each of which is a resistance change element. The sum operator includes an output detector that detects the sum of outputs from the plurality of product operation elements and the resistance change element includes a fuse portion which is disconnected when a malfunction which increases an output current from the resistance change element has occurred in the resistance change element.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 15, 2023
    Assignee: TDK CORPORATION
    Inventor: Tatsuo Shibata
  • Patent number: 11711082
    Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.
    Type: Grant
    Filed: October 10, 2021
    Date of Patent: July 25, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11711988
    Abstract: An aspect of the invention relates to an elementary cell that includes a breakdown layer made of dielectric having a thickness that depends on a breakdown voltage, a device and a non-volatile resistive memory mounted in series, the device including an upper selector electrode, a lower selector electrode, a layer made in a first active material, referred to as active selector layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made in at least one second active material, referred to as active memory layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 25, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Anthonin Verdy
  • Patent number: 11699014
    Abstract: Pathways between reference locations in a physical system are generated based on a layout table. Nodes and edges of the directed graph are associated with cell locations of the layout table. The cell locations define features of the reference locations. Parameters of the nodes and edges are defined based on descriptors recalled from the cells associated with the nodes and edges. The nodes and edges are configured based on the descriptors. Path data regarding potential pathways is generated based on the defined nodes and edges.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 11, 2023
    Assignee: Insight Direct USA, Inc.
    Inventor: Michael Griffin
  • Patent number: 11691020
    Abstract: The implant comprises a tubular body housing an energy harvesting module adapted to convert external stresses applied to the implant into electrical energy, and a rechargeable battery adapted to be charged by the energy harvesting module. During the storage, an external source physically separated from the implant is coupled to the implant rechargeable battery to maintain a minimum battery charge level. An interface circuit of the implant couples surface electrodes to the battery, with switching between: i) a transport and storage configuration where the electrodes are connected to the external source to receive from the latter a battery charging energy and/or to exchange communication signals with the outside through the wire link of the coupling; and ii) a functional configuration in which the surface electrodes are decoupled from the external source after the implant has been implanted.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 4, 2023
    Assignee: Cairdac
    Inventors: Alaa Makdissi, Willy Regnier, An Nguyen-Dinh
  • Patent number: 11684790
    Abstract: The implant comprises a tubular body housing an energy harvesting module adapted to convert external stresses applied to the implant into electrical energy, and a rechargeable battery adapted to be charged by the energy harvesting module. During the storage, an external source physically separated from the implant is coupled to the implant rechargeable battery to maintain a minimum battery charge level. An interface circuit of the implant couples surface electrodes to the battery, with switching between: i) a transport and storage configuration where the electrodes are connected to the external source to receive from the latter a battery charging energy and/or to exchange communication signals with the outside through the wire link of the coupling; and ii) a functional configuration in which the surface electrodes are decoupled from the external source after the implant has been implanted.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 27, 2023
    Assignee: Cairdac
    Inventors: Alaa Makdissi, Willy Regnier, An Nguyen-Dinh
  • Patent number: 11683037
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: June 20, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11652274
    Abstract: The present invention discloses a millimeter wave wireless connector chip, a wireless connector and a signal transmission system, wherein the chip comprises a data interface module, a serial-to-parallel conversion module, a millimeter wave transceiving module and a state machine control module; the data interface module is configured for receiving or sending a data signal; the serial-to-parallel conversion module is configured for converting a parallel signal into a serial signal and sending the serial signal to a wireless transceiving module, and is also configured for receiving the serial signal sent by the millimeter wave transceiving module and converting the received serial signal into a parallel signal; the millimeter wave transceiving module is configured for transceiving data by millimeter waves; and the state machine control module is configured for controlling the serial-to-parallel conversion module and the millimeter wave transceiving module to perform data reception, data sending or data dormancy
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: May 16, 2023
    Assignee: DECO SEMICONDUCTOR (SHENZHEN) CO., LIMITED
    Inventors: Cheng Li, Wenxue Jin
  • Patent number: 11640780
    Abstract: The present disclosure relates to a data driver circuit capable of overcoming a limitation in frequency by correcting a skew between a clock and data even when a frequency and the number of channels are increased, and the data driver circuit according to an aspect may include a shift register configured output sampling signals in response to a clock, a first latch part configured to sample and latch data of each channel in response to each of the sampling signals, and a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a second latch of a second channel belonging to the first latch part and configured to buffer a clock input from the stage of the first channel.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: May 2, 2023
    Assignee: LX SEMICON CO., LTD.
    Inventors: Sung Wan Jung, Sung Je Eom
  • Patent number: 11500793
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Kenji Sakaue, Toshiyuki Furusawa, Shinya Takeda
  • Patent number: 11482266
    Abstract: Methods, systems, and devices for edgeless memory clusters are described. Systems, devices, and techniques are described for eliminating gaps between clusters by creating groups (e.g., domains) of clusters that are active at a given time, and using drivers within inactive clusters to perform array termination functions for abutting active clusters. Tiles on the edges of a cluster may have drivers that operate both for the cluster, and for a neighboring cluster, with circuits (e.g., a multiplexers) on the drivers to enable operations for both clusters.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 11455272
    Abstract: An SoC maintains the full flexibility of a general-purpose microprocessor while providing energy efficiency similar to an ASIC by implementing software-controlled virtual hardware architectures that enable the SoC to function as a virtual ASIC. The SoC comprises a plurality of “Stella” Reconfigurable Multiprocessors (SRMs) supported by a Network-on-a-Chip that provides efficient data transfer during program execution. A hierarchy of programmable switches interconnects the programmable elements of each of the SRMs at different levels to form their virtual architectures. Arithmetic, data flow, and interconnect operations are also rendered programmable. An architecture index” points to a storage location where pre-determined hardware architectures are stored and extracted during program execution. The programmed architectures are able to mimic ASIC properties such as variable computation types, bit-resolutions, data flows, and amount and proportions of compute and data flow operations and sizes.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 27, 2022
    Assignee: Axis Semiconductor, Inc.
    Inventors: Xiaolin Wang, Qian Wu
  • Patent number: 11449459
    Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: September 20, 2022
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Ananth Durbha, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11451229
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Google LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 11442884
    Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 13, 2022
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Andreas Agne, Dominik Lubeley, Heiko Kalte, Marc Schlenger
  • Patent number: 11442736
    Abstract: A method is described for identifying communication-ready data bus subscribers connected to a local bus. The method comprises receiving, at a local bus master, at least one data packet transmitted via the local bus, wherein the at least one data packet received at the local bus master comprises an address of a communication-ready data bus subscriber among a plurality of communication-ready data bus subscribers in the local bus, wherein the communication-ready data bus subscriber is in a sequence of communication-ready data bus subscribers, and mapping of the received address by the local bus master to a relative position of the communication-ready data bus subscriber in the sequence of communication-ready data bus subscribers in the local bus. In addition, a local bus master of the local bus is described.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 13, 2022
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Daniel Jerolm
  • Patent number: 11416227
    Abstract: A method for executing program components on a control unit includes receiving a first program unit and a second program unit; producing a first proxy definition and a second proxy definition, wherein a proxy definition stipulates access to at least one function and/or a memory area of a program unit, wherein the first proxy definition is associated with the first program unit and the second proxy definition is associated with the second program unit; compiling the first program unit and the second program unit to produce a first program component, a second program component, a first proxy component and a second proxy component; and executing the first program component and the second program component on a control unit, wherein the first program component calls and/or uses at least one function of the second program component by using the first proxy component and the second proxy component.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 16, 2022
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventors: Christoph Borchers, Jakob Reuter
  • Patent number: 11409540
    Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 9, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
  • Patent number: 11403108
    Abstract: A processor includes: a memory; an execution pipeline having a plurality of pipeline stages for executing an operation on data provided to the execution pipeline and storing a result of the operation into the memory; a receive pipeline having a plurality of pipeline stages for handling incoming data to the processor and storing the incoming data into memory; context status storage for holding an exception indicator of an exception encountered by the receive pipeline whilst it is handling incoming data; the receive pipeline being configured to determine that an exception has been encountered in one of its pipeline stages and to delay committing the exception indicator to the context status storage until a final one of its pipeline stages and to continue to receive and store incoming data into the memory until the exception indicator has been committed.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 2, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: James Pallister, Jamie Hanlon
  • Patent number: 11378622
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: July 5, 2022
    Assignee: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Patent number: 11362662
    Abstract: Illustrative embodiments provide a mixed programmable and application-specific integrated circuit, a method of using the mixed programmable and application-specific integrated circuit and a method of making the mixed programmable and application-specific integrated circuit. The mixed programmable and application-specific integrated circuit includes at least a portion of a programmable transistor array that is programed after fabrication. The programmable transistor array can include at least another portion that is mask programed during fabrication.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Carl Sechen, Georgios Makris, Thomas Broadfoot
  • Patent number: 11356099
    Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. It is especially important to use an efficient structure, i.e. a structure whose chip area is as small as possible and which is able to realize short and fast signal paths. The task of the present invention is to significantly reduce the effort for the interconnection structures while still maintaining good routeability. This is achieved by the fact that there is no longer a switchbox (SB) on each coordinate position. It is particularly advantageous to arrange the SBs in a chessboard-like manner and also to use two SBs of different sizes which are arranged in a superordinate chessboard structure.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 7, 2022
    Inventor: Michael Gude
  • Patent number: 11334263
    Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Scott J. Weber, David Greenhill, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
  • Patent number: 11314680
    Abstract: Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: April 26, 2022
    Assignee: Raytheon Company
    Inventors: Hrishikesh Shinde, Daryl Coleman
  • Patent number: 11308026
    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. Each processing element can generate an output partial sum based on the arithmetic operations, provide the input to a next processing element of the given row-oriented bus, without the input being processed by a processing element of the row located between the two processing elements that uses a different row-oriented bus. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A Volpe, Vasanta Kumar Palisetti, Thomas Elmer, Kiran K Seshadri, FNU Arun Kumar
  • Patent number: 11309896
    Abstract: A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 19, 2022
    Assignees: KATHOLIEKE UNIVERSITEIT LEUVEN, UNIVERSITÀ DELLA SVIZZERA ITALIANA, ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
    Inventors: Nele Mentens, Francesco Regazzoni, Edoardo Charbon
  • Patent number: 11288220
    Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 29, 2022
    Assignee: Achronix Semiconductor Corporation
    Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
  • Patent number: 11257526
    Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Scott J. Weber, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
  • Patent number: 11251369
    Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 11243251
    Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 8, 2022
    Assignee: SEMITRONIX CORPORATION
    Inventors: Fan Lan, Weiwei Pan, Shenzhi Yang
  • Patent number: 11188497
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 30, 2021
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Patent number: 11183246
    Abstract: A memory device includes a first plane defined in a second wafer stacked on a first wafer; a second plane defined in a third wafer stacked on the second wafer, and overlapping with the first plane in a vertical direction; a first page buffer circuit including a first column driver coupled to bit lines of the first plane and a first column operator; and a second page buffer circuit including a second column driver coupled to bit lines of the second plane and a second column operator. The first column driver is disposed in the second wafer, the second column driver is disposed in the third wafer and overlaps with the first column driver in the vertical direction, and the first and second column operators are disposed in a cell region of the first wafer and overlap with the first and second planes in the vertical direction.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Won Seok Kim, Sang Woo Park
  • Patent number: 11171652
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 9, 2021
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 11159453
    Abstract: By querying a set of fabrics to determine an initiator logged into a fabric in the set of fabrics, a set of accessible fabrics is discovered, an accessible fabric in the set of accessible fabrics accessible to the initiator, an initiator comprising a transceiver connecting a server to a switch, a fabric in the set of fabrics comprising a switch connecting a server to a storage device, the storage device comprising a storage volume. Using a fabric usage policy, a set of allowed fabrics within the set of accessible fabrics is determined. Using the set of allowed fabrics, a storage volume is mapped to a server, the mapping enabling the server to access the storage volume via a fabric in the set of allowed fabrics.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gerald Francis McBrearty
  • Patent number: 11144652
    Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ellery Cochell, Brian S. Martin, Ravi N. Kurlagunda
  • Patent number: 11121021
    Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: September 14, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman
  • Patent number: 11106616
    Abstract: Examples described herein generally relate to a Peripheral Connect Interconnect Express (PCIe) device. An example is a non-transitory memory storing a representation of a design that is to be implemented on a programmable integrated circuit. The design includes a classifier module (CM), a message trap engine module (MTEM), and a configuration space. The CM is capable of receiving a PCIe message and is configured to determine whether the PCIe message is a PCIe Type 1 configuration transaction. The CM is configured to forward the PCIe message to an endpoint device and to the MTEM when the PCIe message is a non-PCIe Type 1 configuration transaction and the PCIe Type 1 configuration transaction, respectively. The MTEM is configured to virtualize a downstream port(s) of a virtual switch and maintain the configuration space. The MTEM is capable of accessing the configuration space in response to the PCIe message.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 31, 2021
    Assignee: XILINX, INC.
    Inventor: Chunhua Wu
  • Patent number: 11101801
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 24, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11088693
    Abstract: A method for mapping a Boolean function to a configurable logic block (CLB). The CLB includes a first plurality of programmable logic cells (PLCs). The Boolean function includes a plurality of digits. Each of the plurality of digits includes a respective hexadecimal value. The method includes mapping the Boolean function to a first PLC of the first plurality of PLCs responsive to the plurality of digits satisfying a first condition. In an exemplary embodiment, the first condition includes at least two digits of the plurality of digits being different and each of the plurality of digits including one of a first hexadecimal digit, a second hexadecimal digit different from the first hexadecimal digit, a bitwise complement of the first hexadecimal digit, and a bitwise complement of the second hexadecimal digit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 10, 2021
    Inventors: Hossein Asadi, Elmira Nezamfar, Zeinab Seifoori
  • Patent number: 11080048
    Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Jesus Corbal, Dan Baum, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil, Raanan Sade
  • Patent number: 11073484
    Abstract: An image acceleration processing device including a field programmable gate array (FPGA) processing platform; and a personal computer (PC). The FPGA processing platform includes: a first fiber interface configured to receive configuration parameters and test commands, and to output test results; a second fiber interface configured to exchange data with the PC; a third fiber interface configured to receive image data and output the configuration parameters and the test commands; a fourth fiber interface configured to control the generation of a screen lighting signal; and a fifth fiber interface configured to control an input/output (IO) light source.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 27, 2021
    Assignee: WUHAN JINGCE ELECTRONIC GROUP CO., LTD.
    Inventors: Changdong Ou, Zhou Wang, Biaohua Deng, Wentian Tang, Linhai Mei, Wenzhong Dong, Bo Li, Moxiao Xu
  • Patent number: 11074970
    Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
  • Patent number: 11061853
    Abstract: A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 13, 2021
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks, Douglas R. Reed
  • Patent number: 11018191
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include replacement gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach