Array (e.g., Pla, Pal, Pld, Etc.) Patents (Class 326/39)
  • Patent number: 10797702
    Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 6, 2020
    Assignee: Altera Corporation
    Inventor: Tony K. Ngai
  • Patent number: 10790830
    Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton
  • Patent number: 10789000
    Abstract: Provided is a variable electronic apparatus including a memory unit, a processing unit and a programmable logic gate device. The memory unit stores configuration data. The processing unit reads the configuration data from the memory unit and determines at least one control mode based on the configuration data. The programmable logic gate device includes a plurality of function modules and at least one switching unit. When the control mode includes a function module selecting mode and a signal line switching mode, the processing unit selects or activates the function modules of the programmable logic gate device based on the function module selecting mode, and the switching unit of the programmable logic gate device dynamically modifies or adaptably adjusts a bus of the function module selected by the processing unit and a corresponding external signal line based on the signal line switching mode.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 29, 2020
    Assignee: AEWN TECHNOLOGIES CO., LTD.
    Inventor: Ming-Lun Shao
  • Patent number: 10776183
    Abstract: An information processing apparatus includes, a programmable circuit that includes multiple areas into which logics are capable of being programmed, a memory, and a processor configured to, receive a request including information concerning a first process and a second process, calculate a first throughput corresponding to the first process and a second throughput corresponding to the second process based on data used in each of the first process and the second process, determine a first number of areas in which the first process is performed and a second number of areas in which the second process is performed, and program first logics to perform the first process in first areas among the multiple areas, and program second logics to perform the second process in second areas among the multiple areas, the first areas corresponding to the first number, the second areas corresponding to the second number.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hidetoshi Matsumura, Yasuhiro Watanabe
  • Patent number: 10754793
    Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10754993
    Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 25, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Kenneth R. Weidele, Kenneth F. McKinney, Christopher H. Meawad, Tim Manestitaya, Allan T. Hilchie, Timothy D. Schaffner
  • Patent number: 10725102
    Abstract: An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Semitronix Corporation
    Inventor: Fan Lan
  • Patent number: 10726181
    Abstract: A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 28, 2020
    Assignee: XILINX, INC.
    Inventors: Martin L. Voogel, Trevor J. Bauer, Henri Fraisse
  • Patent number: 10720927
    Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 21, 2020
    Assignee: Altera Corporation
    Inventor: Laura Reese
  • Patent number: 10715144
    Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Sergey Gribok, Gregg Baeckler, Martin Langhammer
  • Patent number: 10706898
    Abstract: A semiconductor apparatus may include: a pad unit including a plurality of pads; a memory cell array coupled to the pad unit through input/output signal lines; and a pad configuration control circuit configured to change a pad configuration of the pad unit by dividing the plurality of pads into a plurality of groups and setting the plurality of groups to different modes, respectively.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Myoung Seo Kim, Seung Yong Lee, Young Pyo Joo
  • Patent number: 10691634
    Abstract: Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 23, 2020
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10691860
    Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 23, 2020
    Assignee: RAMBUS INC.
    Inventors: Lap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
  • Patent number: 10686448
    Abstract: An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 16, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
  • Patent number: 10680616
    Abstract: An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Geoffrey R. Tate, Cheng C. Wang
  • Patent number: 10671148
    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 2, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
  • Patent number: 10637478
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 28, 2020
    Inventor: Jonathan Ross
  • Patent number: 10620998
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 14, 2020
    Assignee: ThroughPuter, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 10608638
    Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 31, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10600772
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10585615
    Abstract: An apparatus may include a virtual flash device configured to emulate a flash memory device. The virtual flash device may include a flash interface configured to communicate with a flash controller, an address translation module configured to translate memory addresses from a flash based memory space to another memory space of another memory, a metadata and control module configured to manage metadata from the emulation of the flash memory device, and a non-flash memory controller configured to communicate with the other memory.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Seagate Technology LLC
    Inventors: Prasad Ramchandra Kadam, Sachin Sudhir Jagtap, Kedar Patankar
  • Patent number: 10545472
    Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first output and a second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system includes multiple multiplexing units and multiple data acquisition units receiving multiple data streams from multiple machines in the industrial environment.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 28, 2020
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10516397
    Abstract: In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 24, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bert Sullam, Warren Snyder, Haneef Mohammed
  • Patent number: 10503559
    Abstract: A task mapping method of a NoC semiconductor device includes assigning a first task of a plurality of tasks for node control of the NoC semiconductor device to a first node of a first chip; computing tag values of second tasks of the plurality of tasks which are not assigned to the first node; and assigning the second tasks to a second node according to the tag values.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: December 10, 2019
    Assignees: SK hynix Inc., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Tae Hee Han, Hyun Joong Kim
  • Patent number: 10467364
    Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Patent number: 10453730
    Abstract: A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Oh Seung Min
  • Patent number: 10454475
    Abstract: It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Shunpei Yamazaki
  • Patent number: 10454480
    Abstract: An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Silicon Mobility
    Inventors: Grégorie Martin, David Cavalli, Fabian Firmin
  • Patent number: 10431306
    Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinichi Yasuda, Masato Oda, Kosuke Tatsumura
  • Patent number: 10416638
    Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first and second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system is configured to manage data collection bands. The local data collection system includes a neural net expert system using intelligent management of the data collection bands.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 17, 2019
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10416637
    Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first and second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system is configured to manage data collection bands. The local data collection system includes a neural net expert system using intelligent management of the data collection bands.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 17, 2019
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10411711
    Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: September 10, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Anthony Kozaczuk, Cheng C. Wang, Abhijit M. Abhyankar
  • Patent number: 10410691
    Abstract: A non-volatile memory includes a sense amplifier, a switching element and a power switching circuit. A first sub-cell is connected with a word line, a bit line and a source line. A second sub-cell is connected with the word line, an inverted bit line and an inverted source line. During a read cycle, an activation period of the word line contains a first period and a second period. In the first period, the first sub-cell generates a first read current to a first current path, and the second sub-cell generates a second read current to a second current path. The first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 10, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 10402342
    Abstract: Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 3, 2019
    Assignee: Aspiring Sky Co., Limited
    Inventors: Zhijiong Luo, Xiaoming Jin, Shu Wang
  • Patent number: 10404257
    Abstract: An information processing apparatus includes a processor for an arithmetic processing and a reconfiguration circuit for the arithmetic processing, wherein the reconfiguration circuit includes a plurality of blocks, an inter-block FIFO that couples the blocks, and a common region that is used for a reconfiguration that changes a size of the inter-block FIFO.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Katayama
  • Patent number: 10396799
    Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 27, 2019
    Assignee: XILINX, INC.
    Inventors: Vishwak R Manda, Sree RKC Saraswatula, Santosh Yachareni, Shidong Zhou, Jing Jing Chen, Michael Tsivyan
  • Patent number: 10374608
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 6, 2019
    Inventor: Jonathan Ross
  • Patent number: 10366737
    Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10355909
    Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Eng Ling Ho, Sean Atsatt, Chiew Siang Wong, Chin Hai Ang, Rob Pelt, Ee Mei Ooi
  • Patent number: 10348308
    Abstract: An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: July 9, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
  • Patent number: 10348355
    Abstract: A wearable gesture recognition device is disclosed that provides gesture recognition for gestures that may include a hold or steady-state component, and may account and adapt for real-time fit-level changes. The wearable gesture recognition device may integrate a photoplethysmographic (PPMG) and a piezoelectric (PZE) sensor such that respective sensor signals may be used individually, or in concert for gesture recognition. Thus the wearable gesture recognition device generally disclosed herein may advantageously perform gesture recognition through the fusion of PPMG and PZE signals. To support continuous gesture recognition, the wearable gesture recognition device may use a low-power activity detection scheme that analyzes a PZE signal prior to higher-power gesture classification. Moreover, the wearable gesture recognition device may provide power management by controlling a duty-cycle of the PPMG sensor without necessarily reducing recognition performance.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Jose Rodrigo Camacho Perez, Hector Raul Moncada Gonzalez, Hector Alfonso Cordourier Maruri, Julio Cesar Zamora Esquivel, Paulo Lopez Meyer, Alejandro Ibarra Von Borstel
  • Patent number: 10339979
    Abstract: An embodiment includes an apparatus comprising: power supply pins to couple to a power supply; a protection block, including a first transistor, to: (a) determine whether voltage from the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first and second function blocks; and the first function block, coupled to the protection block and the power supply pins, including a second transistor and at least one fuse that corresponds to a security key; wherein the first transistor is at least one of: (a) connected in series with at least one other transistor, and (b) having a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor. Other embodiments are described herein.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Seyed-Abdollah Aftabjahani, Amitabh Das
  • Patent number: 10341795
    Abstract: The present disclosure is generally directed to audio visualization methods for visual pattern recognition of sound. In particular, the present disclosure is directed to plotting amplitude intensity as brightness/saturation and phase-cycles as hue-variations to create visual representations of sound.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 2, 2019
    Assignee: The Curators of the University of Missouri
    Inventors: Philip Fraundorf, Stephen Wedekind, Wayne Garver
  • Patent number: 10312911
    Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 4, 2019
    Assignee: AnDAPT, Inc.
    Inventors: John Birkner, Kapil Shankar, Herman Cheung, Patrick J. Crotty, Ranajit Ghoman
  • Patent number: 10305486
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10303192
    Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Alexandre Pons
  • Patent number: 10282338
    Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 7, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Liewei Bao, Ian Rudolf Bratt
  • Patent number: 10268464
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • Patent number: 10262732
    Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 16, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Seow Fong Lim, Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung
  • Patent number: 10230368
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Takeshi Aoki