Array (e.g., Pla, Pal, Pld, Etc.) Patents (Class 326/39)
  • Patent number: 10431306
    Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinichi Yasuda, Masato Oda, Kosuke Tatsumura
  • Patent number: 10416638
    Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first and second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system is configured to manage data collection bands. The local data collection system includes a neural net expert system using intelligent management of the data collection bands.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 17, 2019
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10416637
    Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first and second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system is configured to manage data collection bands. The local data collection system includes a neural net expert system using intelligent management of the data collection bands.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 17, 2019
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10411711
    Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: September 10, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Anthony Kozaczuk, Cheng C. Wang, Abhijit M. Abhyankar
  • Patent number: 10410691
    Abstract: A non-volatile memory includes a sense amplifier, a switching element and a power switching circuit. A first sub-cell is connected with a word line, a bit line and a source line. A second sub-cell is connected with the word line, an inverted bit line and an inverted source line. During a read cycle, an activation period of the word line contains a first period and a second period. In the first period, the first sub-cell generates a first read current to a first current path, and the second sub-cell generates a second read current to a second current path. The first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 10, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 10402342
    Abstract: Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 3, 2019
    Assignee: Aspiring Sky Co., Limited
    Inventors: Zhijiong Luo, Xiaoming Jin, Shu Wang
  • Patent number: 10404257
    Abstract: An information processing apparatus includes a processor for an arithmetic processing and a reconfiguration circuit for the arithmetic processing, wherein the reconfiguration circuit includes a plurality of blocks, an inter-block FIFO that couples the blocks, and a common region that is used for a reconfiguration that changes a size of the inter-block FIFO.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Katayama
  • Patent number: 10396799
    Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 27, 2019
    Assignee: XILINX, INC.
    Inventors: Vishwak R Manda, Sree RKC Saraswatula, Santosh Yachareni, Shidong Zhou, Jing Jing Chen, Michael Tsivyan
  • Patent number: 10374608
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 6, 2019
    Inventor: Jonathan Ross
  • Patent number: 10366737
    Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10355909
    Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Eng Ling Ho, Sean Atsatt, Chiew Siang Wong, Chin Hai Ang, Rob Pelt, Ee Mei Ooi
  • Patent number: 10348308
    Abstract: An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: July 9, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
  • Patent number: 10348355
    Abstract: A wearable gesture recognition device is disclosed that provides gesture recognition for gestures that may include a hold or steady-state component, and may account and adapt for real-time fit-level changes. The wearable gesture recognition device may integrate a photoplethysmographic (PPMG) and a piezoelectric (PZE) sensor such that respective sensor signals may be used individually, or in concert for gesture recognition. Thus the wearable gesture recognition device generally disclosed herein may advantageously perform gesture recognition through the fusion of PPMG and PZE signals. To support continuous gesture recognition, the wearable gesture recognition device may use a low-power activity detection scheme that analyzes a PZE signal prior to higher-power gesture classification. Moreover, the wearable gesture recognition device may provide power management by controlling a duty-cycle of the PPMG sensor without necessarily reducing recognition performance.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Jose Rodrigo Camacho Perez, Hector Raul Moncada Gonzalez, Hector Alfonso Cordourier Maruri, Julio Cesar Zamora Esquivel, Paulo Lopez Meyer, Alejandro Ibarra Von Borstel
  • Patent number: 10339979
    Abstract: An embodiment includes an apparatus comprising: power supply pins to couple to a power supply; a protection block, including a first transistor, to: (a) determine whether voltage from the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first and second function blocks; and the first function block, coupled to the protection block and the power supply pins, including a second transistor and at least one fuse that corresponds to a security key; wherein the first transistor is at least one of: (a) connected in series with at least one other transistor, and (b) having a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor. Other embodiments are described herein.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Seyed-Abdollah Aftabjahani, Amitabh Das
  • Patent number: 10341795
    Abstract: The present disclosure is generally directed to audio visualization methods for visual pattern recognition of sound. In particular, the present disclosure is directed to plotting amplitude intensity as brightness/saturation and phase-cycles as hue-variations to create visual representations of sound.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 2, 2019
    Assignee: The Curators of the University of Missouri
    Inventors: Philip Fraundorf, Stephen Wedekind, Wayne Garver
  • Patent number: 10312911
    Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 4, 2019
    Assignee: AnDAPT, Inc.
    Inventors: John Birkner, Kapil Shankar, Herman Cheung, Patrick J. Crotty, Ranajit Ghoman
  • Patent number: 10305486
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10303192
    Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Alexandre Pons
  • Patent number: 10282338
    Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 7, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Liewei Bao, Ian Rudolf Bratt
  • Patent number: 10268464
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • Patent number: 10262732
    Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 16, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Seow Fong Lim, Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung
  • Patent number: 10230368
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Takeshi Aoki
  • Patent number: 10223318
    Abstract: Examples provided herein relate to hot plugging PCIe cards. For example, a field programmable gate array (“FPGA”) communicably coupled to a PCIe bus may detect a new PCIe card physically connected to the PCIe bus. The FPGA may access configuration information stored by the FPGA that is associated with the PCIe bus. The FPGA may determine, based on the accessed configuration information, whether to facilitate connection of the new PCIe card to the PCIe bus. Responsive to determining that connection of the new PCIe card to the PCIe bus should be facilitated, the new PCIe card may be trained to communicate with the PCIe bus and an upstream device communicably coupled to the PCIe bus.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Srivani Kor Koriginja Ramaswamy, Yiling Zhang, Hoang Thanh Nguyen
  • Patent number: 10217512
    Abstract: A neural network unit cell circuit includes multiple floating gate transistors, each of the floating gate transistors having a first source/drain adapted for connection to a common bit line coupled with the unit cell circuit and having a gate adapted for connection to a corresponding one of a plurality of word lines coupled with the unit cell circuit. The unit cell further includes a resistor network having a plurality of resistors connected in a series ladder arrangement, with each node between adjacent resistors operatively connected to a second source/drain of a corresponding one of the floating gate transistors. The resistor network has a first terminal connected to a first voltage source. A readout transistor in the unit cell has a gate coupled with a second terminal of the resistor network, and has first and second source/drains generating an output voltage of the unit cell.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10177766
    Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 8, 2019
    Assignee: Altera Corporation
    Inventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
  • Patent number: 10170172
    Abstract: A logic circuit may include at least one magnetic tunnel junction device including a first layer configured to receive a particular input signal and a second layer connected to a node, and an inverter connected to the node and configured to generate an output signal by inverting a signal of the node, wherein the inverter includes a transistor on a substrate, and the at least one magnetic tunnel junction device is on an upper portion of the transistor. The at least one magnetic tunnel junction device may include first and second magnetic tunnel junction devices configured to receive first and second input signals, respectively. The logic circuit may include a magnetic tunnel junction device and a reference resistor configured to receive a second input signal, the reference resistor connected to the node, the reference resistor having a reference resistance. The logic circuit may be included in an apparatus.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Min Lee, Hyunsung Jung
  • Patent number: 10162000
    Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 25, 2018
    Assignee: NXP B.V.
    Inventor: Tom Waayers
  • Patent number: 10164880
    Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma, Robert P. Adler
  • Patent number: 10162921
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10148271
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 4, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10120921
    Abstract: A system, method, and computer-readable storage medium configured to facilitate the parallel transfer of Structured Query Language (SQL) data to a software framework.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 6, 2018
    Assignee: Mastercard International Incorporated
    Inventor: Joshua A. Allbright
  • Patent number: 10091125
    Abstract: Multiple TCP/IP stack processors on a host. The multiple TCP/IP stack processors are provided independently of TCP/IP stack processors implemented by virtual machines on the host. The TCP/IP stack processors provide multiple different default gateway addresses for use with multiple processes. The default gateway addresses allow a service to communicate across an L3 network. Processes outside of virtual machines that utilize the TCP/IP stack processor on a first host can benefit from using their own gateway, and communicate with their peer process on a second host, regardless of whether the second host is located within the same subnet or a different subnet. The multiple TCP/IP stack processors can use separately allocated resources. Separate TCP/IP stack processors can be provided for each of multiple tenants on the host. Separate loopback interfaces of multiple TCP/IP stack processors can be used to create separate containment for separate sets of processes on a host.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 2, 2018
    Assignee: NICIRA, INC.
    Inventors: Nithin B. Raju, Ganesan Chandrashekhar, Gopakumar Pillai
  • Patent number: 10089259
    Abstract: A data processing system is disclosed that includes an in-line accelerator and a processor. The system can be extended to include an in-line accelerator and system of multi-level accelerators and a processor. The in-line accelerator receives the incoming data elements and begins processing. Upon premature termination of the execution, the in-line accelerator transfers the execution to a processor (or the next level accelerator in a multi-level acceleration system). Transfer of execution includes transferring of data and control. The processor (or the next accelerator) either continues the execution of the in-line accelerator from the bailout point or restarts the execution. The necessary data must be transferred to the processor (or the next accelerator) to complete the execution.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 2, 2018
    Assignee: Bigstream Solutions, Inc.
    Inventor: Maysam Lavasani
  • Patent number: 10075163
    Abstract: A contact sensing device includes: a first electrode and a second electrode facing each other, a drive detection circuit of an electrostatic capacitance type, a first switching circuit that implements switching between connection and disconnection between the first electrode and ground, and a second switching circuit that implements switching between connection and disconnection between the first electrode and the second electrode. The drive detection circuit implements switching between a first state and a second state and detects an electrostatic capacitance change in the first state and an electrostatic capacitance change in the second state.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: September 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shigeki Nishiyama
  • Patent number: 10050629
    Abstract: A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 14, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Hagop Nazarian
  • Patent number: 10025364
    Abstract: Provided is a method for measuring power of a graphics processing unit. The method includes changing a utilization of the graphics processing unit through an application programming interface (API), measuring and storing the utilization or a driving frequency of the graphics processing unit for each trace time, measuring and storing power consumption of the graphics processing unit for each trace time, and synchronizing the utilization of the graphics processing unit with the power consumption according to a stored trace time and calculating a power coefficient for each driving frequency with reference to synchronized information.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 17, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Young-Joo Kim
  • Patent number: 10027327
    Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 17, 2018
    Assignee: Altera Corporation
    Inventor: David Lewis
  • Patent number: 10002219
    Abstract: A method for placing a parallel multiplier with a placement and routing tool includes receiving a datapath netlist about the parallel multiplier, extracting locations of primary input cells and primary output cells from the datapath netlist using a structure analysis module, mapping the primary input cells and the primary output cells on a specific array using the placement and routing tool, and arranging columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells. The columns are arranged using the placement and routing tool. The size of the specific array is determined according to a number of the primary input cells.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 19, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungmin Bae, Hyung-Ock Kim
  • Patent number: 9973194
    Abstract: An integrated circuit comprising programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array, wherein each logic tile includes logic circuitry and I/O connected in an interconnect network via multiplexers. A first logic tile includes (i) a first portion of a perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry and (ii) a second portion of a perimeter which is interior to such circuitry's periphery, wherein memory I/O is disposed on the second portion of the perimeter of the first logic tile. A second logic tile includes a second portion of a perimeter which is interior to the programmable/configurable logic circuitry's periphery and opposes the first logic tile's perimeter. Memory array(s), located between the second portions of the perimeters of the first and second logic tiles, is/are coupled to memory I/O of at least the first logic tile.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 15, 2018
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Geoffrey R. Tate, Cheng C. Wang
  • Patent number: 9960772
    Abstract: A semiconductor device of an embodiment includes: a logical block including at least one first input terminal; at least two first output terminal; a first wiring line group; a second and third wiring line groups including a plurality of shorter wiring lines than wiring lines of the first wiring line group; a fourth and fifth wiring line groups; a first to fourth switch circuits; a first logical element including second and third input terminals connected to at least one of wiring lines of the fourth wiring line group, and a second output terminal connected to one of the at least two first output terminals; and a second logical element including fourth and fifth input terminals connected to at least one of the wiring lines of the fifth wiring line group, and a third output terminal connected to another of the at least two first output terminals.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 1, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mizuki Ono, Shinichi Yasuda
  • Patent number: 9954532
    Abstract: An integrated circuit according to an embodiment includes: a first block including a first logic block configured to perform a logical operation, a first switch block circuit configured to control connection and non-connection with the first logic block, and a second switch block circuit configured to control connection and non-connection with the first logic block; and a second block including a second logic block configured to perform a logical operation, a third switch block circuit configured to control connection and non-connection with the second logic block, and a fourth switch block circuit configured to control connection and non-connection with the second logic block, wherein the first switch block circuit is mutually connected with the third and fourth switch block circuits, and the second switch block circuit is mutually connected with the third and fourth switch block circuits.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masato Oda
  • Patent number: 9954530
    Abstract: An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 24, 2018
    Assignee: Altera Corporation
    Inventors: Christopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
  • Patent number: 9954533
    Abstract: According to one general aspect, an apparatus may include a memory array comprising a plurality of memory sub-arrays. At least one of the sub-arrays may be arranged as a reconfigurable look-up table. The reconfigurable look-up table may include: a plurality of memory cells configured to store data, a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals, a local line selector configured to select a sub-set of the row of memory cells based upon at least one input signal.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mingyu Gao, Hongzhong Zheng, Krishna T. Malladi
  • Patent number: 9929979
    Abstract: A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 27, 2018
    Assignee: ANALOG DEVICES, INC.
    Inventor: Michael C. St. Germain
  • Patent number: 9912337
    Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 6, 2018
    Assignee: Altera Corporation
    Inventors: Woi Jie Hooi, Kok Heng Choe
  • Patent number: 9912336
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: March 6, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 9904646
    Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 27, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Michael Simmons
  • Patent number: 9882840
    Abstract: A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: January 30, 2018
    Assignee: ANALOG DEVICES, INC.
    Inventor: Michael C. St. Germain
  • Patent number: 9866219
    Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: January 9, 2018
    Assignees: MEISEI GAKUEN, BUFFALO MEMORY CO., LTD.
    Inventors: Kanji Otsuka, Yoichi Sato, Takayuki Okinaga, Shuichiro Azuma
  • Patent number: 9847070
    Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: December 19, 2017
    Assignee: Apple Inc.
    Inventors: Kwang Soon Park, Chun-Yao Huang, Shih Chang Chang