Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.

Abstract: Aspects of the present disclosure are directed to voltage drop compensation for power supplies. One method includes sensing each voltage, via a voltage sensor, of a plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor for at least one of the plurality of voltages, receiving, at a voltage manager, data for a number of characteristics of the circuitry components, and selecting a correction voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages and data for at least one of the characteristics of the circuitry components.

Abstract: An IC includes a first set of core logic configured to convert data between a single stream and a double stream, and a first data I/O block on a first side of the first set of core logic. The first data I/O block interfaces with the first set of core logic and a DRAM. The IC further includes a second set of core logic configured to process CA information, and a first CA I/O subblock on a second side of the first set of core logic. The first CA I/O subblock interfaces with the second set of core logic and the DRAM. The IC further includes a first set of power switches adjacent at least one side of the first CA I/O subblock. The first set of power switches is coupled to the first set of core logic and the second set of core logic.

Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

Abstract: Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: An input circuit of a flip-flop includes: a first gate strip, a second gate strip and a third gate strip. The first gate strip is a co-gate terminal of a first PMOS and a first NMOS; the second gate strip is disposed immediately adjacent to the first gate strip, and a co-gate terminal of a second PMOS and a second NMOS. The first PMOS and the second PMOS share a doping region as a co-source terminal. The first NMOS and the second NMOS share a doping region as a co-source terminal. The third gate strip is disposed immediately adjacent to the second gate strip. The third gate strip is a co-gate terminal of a third PMOS and a third NMOS. The second PMOS and the third PMOS share a doping region as a co-drain terminal. The second NMOS and the third NMOS share a doping region as a co-drain terminal.

Abstract: A bidirectional serial communication interface comprising a slave powered by a master connected to the slave via a signal line and a return line is disclosed. The master includes a master switch inserted in a line connecting a supply voltage to the signal line and a transceiver transmitting binary signals by opening and closing the master switch and receiving binary signals whilst the master switch is open. The slave includes an energy storage charged via the signal line and providing an internal power supply; a pull-up switch inserted in a line connecting the signal line to the internal power supply; a pull-down switch inserted in a line connecting the signal line to the return line; and a transceiver transmitting binary signals by opening and closing the pull-up and the pull-down switch whilst the master switch is open and receiving binary signals whilst the pull-up and the pull-down switch are open.

Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, and where the third layer includes material other than silicon.

Abstract: Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.

Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said second level comprises at least one Phase Lock Loop (“PLL) circ

Abstract: A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

Abstract: A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.

Abstract: A method for component authentication includes delaying an input signal along a first propagation path and a second propagation path, each propagation path including a same number of delay stages. A plurality of control inputs alters the first propagation path to include at least one delay stage from the second propagation path, and alters the second propagation path to include at least one delay stage from the first propagation path. A time difference between a first output of the first propagation path and a second output of the second propagation path is quantized into a plurality of time bins represented by a multi-bit output. The multi-bit output is transformed with a non-linear transform to provide a response output.

Abstract: A transmission module includes an electrically insulative substrate body, a first card edge connector provided at a first end of the substrate body, a second card edge connector provided at a second end of the substrate body, a circuit element mounted on the substrate body, a control element mounted on the substrate body and provided with a built-in memory which controls the circuit element, a first wiring pattern formed on the substrate body for connecting an electrode of the first card edge connector and the control element together, and a second wiring pattern formed on the substrate body for connecting an electrode of the second card edge connector and the control element together.

Abstract: In some examples, a first delay path and a second delay path may each be configured to receive a signal as an input signal at the same time, propagate the input a plurality of MRAM cells, and output the propagated input signal for an arbiter. The arbiter may be configured to output a response value based at least in part on a relative order of arrival of the propagated input signals from the first and second delay paths.

Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

Abstract: Proposed is a training and simulation device for electric functional processes in electric, electromechanical and electrofluidic systems, with a controller (14) for the simulation and visual reproduction of system components (25-31) on a display (11), and with electric terminals (13) located adjacent to the display (11) for cable connection to hardware components of the system, wherein optical inputs and/or outputs of the simulated system components on the display (11) are assigned to at least a part of the terminals (13) and wherein the controller (14) comprises means for generating electric voltages at the terminals (13) of assigned outputs of the simulated system components (31) and/or for generating reactions of the simulated system components (25-30) in dependence on voltages externally applied to terminals (13) assigned to inputs of said simulated system components.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.

Abstract: An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.

Abstract: A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

Abstract: Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.

Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Abstract: The present invention provides for a method and circuit of an integrated circuit (IC) having dual row input/output (I/O). The circuit having a plurality of dual I/Os including an upper row of I/O and a lower row of I/O, with logic arranged in communication between the upper and the lower rows of the dual row I/O. The connectivity with the logic circuits of the present invention therefore provides for improving reliability and performance through more similar and uniform pathway connections. Advantageously, the present invention also provides for the reallocation of valuable footprint space as the logic is embedded within the dual row I/O thereby creating additional footprint space for further performance and other beneficial gain where interconnects as between the physical layer (PHY) logic and I/O cells are generally similar in length.

Abstract: Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups.

Abstract: A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.

Abstract: A logic module includes a device for implementing a logic function the device including at least one input and at least one output, the output at least partially representing the result of the logic function; at least one first element including at least one resistance state, at least one second element formed by a bipolar resistive memory; the first element and the second element having a common electrode connected to the output.

Abstract: A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.

Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.

Abstract: Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: Systems and methods can perform automatic computation developed using carbon nanotubes and graphene nanoribbons and/or InSb p-n bilayer channel avalanche diodes and wires. Spin logic can provide improvements in speed, power, and area, promising to be a high-performance logic family for the next generation of computing. The systems and methods can replace CMOS, for example, for general computing applications.

Abstract: A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A semiconductor device including a PLD which can increase the execution speed of an application with low power consumption is provided. The semiconductor device includes a programmable logic device and a processor which is not dynamically reconfigured. A memory element of the programmable logic device stores a plurality of pieces of configuration data determined to have high frequency of use by a memory module among configuration data corresponding to a thread. The memory element includes a storage element and a switch in each of a plurality of memory cells. The switch is used for supplying charge whose amount is determined by the plurality of pieces of stored configuration data to the storage element, retaining the charge in the storage element, and discharging the charge from the storage element.