Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/47)
  • Patent number: 10312918
    Abstract: A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 4, 2019
    Assignees: HIGH PERFORMANCE DATA STORAGE AND PROCESSING CORPORATION, SHARIF UNIVERSITY OF TECHNOLOGY
    Inventors: Hossein Asadi, Zahra Ebrahimi, Behnam Khaleghi
  • Patent number: 10038445
    Abstract: A method for component authentication includes delaying an input signal along a first propagation path and a second propagation path, each propagation path including a same number of delay stages. A plurality of control inputs alters the first propagation path to include at least one delay stage from the second propagation path, and alters the second propagation path to include at least one delay stage from the first propagation path. A time difference between a first output of the first propagation path and a second output of the second propagation path is quantized into a plurality of time bins represented by a multi-bit output. The multi-bit output is transformed with a non-linear transform to provide a response output.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 31, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeremy Rice, Rory Buchanan
  • Patent number: 9877388
    Abstract: A transmission module includes an electrically insulative substrate body, a first card edge connector provided at a first end of the substrate body, a second card edge connector provided at a second end of the substrate body, a circuit element mounted on the substrate body, a control element mounted on the substrate body and provided with a built-in memory which controls the circuit element, a first wiring pattern formed on the substrate body for connecting an electrode of the first card edge connector and the control element together, and a second wiring pattern formed on the substrate body for connecting an electrode of the second card edge connector and the control element together.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 23, 2018
    Assignee: HITACHI METALS, LTD.
    Inventors: Akira Ogura, Kinya Yamazaki, Masataka Sato, Shinji Komatsuzaki
  • Patent number: 9712330
    Abstract: In some examples, a first delay path and a second delay path may each be configured to receive a signal as an input signal at the same time, propagate the input a plurality of MRAM cells, and output the propagated input signal for an arbiter. The arbiter may be configured to output a response value based at least in part on a relative order of arrival of the propagated input signals from the first and second delay paths.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: July 18, 2017
    Assignee: Honeywell International Inc.
    Inventor: Michael A. Smith
  • Patent number: 9625523
    Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Saman M. I. Adham
  • Patent number: 9620031
    Abstract: Proposed is a training and simulation device for electric functional processes in electric, electromechanical and electrofluidic systems, with a controller (14) for the simulation and visual reproduction of system components (25-31) on a display (11), and with electric terminals (13) located adjacent to the display (11) for cable connection to hardware components of the system, wherein optical inputs and/or outputs of the simulated system components on the display (11) are assigned to at least a part of the terminals (13) and wherein the controller (14) comprises means for generating electric voltages at the terminals (13) of assigned outputs of the simulated system components (31) and/or for generating reactions of the simulated system components (25-30) in dependence on voltages externally applied to terminals (13) assigned to inputs of said simulated system components.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: April 11, 2017
    Assignee: FESTO AG & CO. KG
    Inventor: Mathias Schietinger
  • Patent number: 9503090
    Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John A. Fifield
  • Patent number: 9459651
    Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 4, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lior Moheban, Avi Elazary, Amir Nave, Noam Sivan
  • Patent number: 9419624
    Abstract: An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 16, 2016
    Assignee: XILINX, INC.
    Inventor: Austin H. Lesea
  • Patent number: 9172378
    Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 27, 2015
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Gregg William Baeckler, Jinyong Yuan, Chris Wysocki, Pouyan Djahani
  • Patent number: 9083339
    Abstract: Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: July 14, 2015
    Assignee: Atmel Corporation
    Inventors: Laurentiu Birsan, Stein Danielsen
  • Patent number: 9030227
    Abstract: A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventor: David Cashman
  • Patent number: 9024656
    Abstract: Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 5, 2015
    Inventor: Mark B. Johnson
  • Publication number: 20150116000
    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
    Type: Application
    Filed: December 31, 2014
    Publication date: April 30, 2015
    Inventors: Takeshi Aoki, Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 9018977
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 28, 2015
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Herman Schmit
  • Patent number: 9018979
    Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Warren Snyder, Bert Sullam, Haneef Mohammed
  • Patent number: 9007092
    Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa
  • Patent number: 9007095
    Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 9007093
    Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 8996906
    Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 31, 2015
    Assignee: Tabula, Inc.
    Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
  • Patent number: 8994404
    Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 8981813
    Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: March 17, 2015
    Assignee: Agate Logic, Inc.
    Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
  • Patent number: 8981814
    Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 17, 2015
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 8975919
    Abstract: The present invention provides for a method and circuit of an integrated circuit (IC) having dual row input/output (I/O). The circuit having a plurality of dual I/Os including an upper row of I/O and a lower row of I/O, with logic arranged in communication between the upper and the lower rows of the dual row I/O. The connectivity with the logic circuits of the present invention therefore provides for improving reliability and performance through more similar and uniform pathway connections. Advantageously, the present invention also provides for the reallocation of valuable footprint space as the logic is embedded within the dual row I/O thereby creating additional footprint space for further performance and other beneficial gain where interconnects as between the physical layer (PHY) logic and I/O cells are generally similar in length.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Tobing Soebroto
  • Patent number: 8970251
    Abstract: Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8963580
    Abstract: A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 24, 2015
    Assignees: Samsung Electronics Co., Ltd., University of Seoul Industry Cooperation Foundation
    Inventors: Hyun-sik Choi, Ho-jung Kim, Ki-chul Kim, Jai-kwang Shin, Joong-ho Choi, Hyung-su Jeong
  • Patent number: 8957398
    Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: February 17, 2015
    Assignee: eASIC Corporation
    Inventors: Alexander Andreev, Sergey Gribok, Ranko L. Scepanovic, Phey-Chuin Tan, Chee-Wei Kung
  • Publication number: 20150035560
    Abstract: A logic module includes a device for implementing a logic function the device including at least one input and at least one output, the output at least partially representing the result of the logic function; at least one first element including at least one resistance state, at least one second element formed by a bipolar resistive memory; the first element and the second element having a common electrode connected to the output.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Inventors: Julien Buckley, Haykel Ben Jamaa
  • Patent number: 8947120
    Abstract: A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Gregory D. Roberts, Robert Kenney, James De Leon
  • Patent number: 8941409
    Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Tabula, Inc.
    Inventors: Martin Voogel, Steven Teig, Trevis Chandler
  • Patent number: 8917111
    Abstract: Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: December 23, 2014
    Assignee: Xilinx Inc.
    Inventor: Kiran S. Puranik
  • Patent number: 8912820
    Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: December 16, 2014
    Assignee: Tabula, Inc.
    Inventors: Randy R. Huang, Martin Voogel, Jingcao Hu, Steven Teig
  • Publication number: 20140361808
    Abstract: Systems and methods can perform automatic computation developed using carbon nanotubes and graphene nanoribbons and/or InSb p-n bilayer channel avalanche diodes and wires. Spin logic can provide improvements in speed, power, and area, promising to be a high-performance logic family for the next generation of computing. The systems and methods can replace CMOS, for example, for general computing applications.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Joseph S. Friedman, Bruce W. Wessels, Alan V. Sahakian
  • Patent number: 8901961
    Abstract: A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Arifur Rahman, Curt Wortman
  • Patent number: 8895408
    Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: November 25, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 8896345
    Abstract: A semiconductor device including a PLD which can increase the execution speed of an application with low power consumption is provided. The semiconductor device includes a programmable logic device and a processor which is not dynamically reconfigured. A memory element of the programmable logic device stores a plurality of pieces of configuration data determined to have high frequency of use by a memory module among configuration data corresponding to a thread. The memory element includes a storage element and a switch in each of a plurality of memory cells. The switch is used for supplying charge whose amount is determined by the plurality of pieces of stored configuration data to the storage element, retaining the charge in the storage element, and discharging the charge from the storage element.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takahiro Fukutome
  • Publication number: 20140340117
    Abstract: A signal processing device is produced. The signal processing device including a first transistor with high off-state resistance, a second transistor which controls conduction between two different nodes, a capacitor which holds electric charge, and a current control element such as a transistor or a resistor. The first node to which a gate of the second transistor and a second electrode of the current control element are connected, and the second node to which one of a source and a drain of the first transistor, a first electrode of the capacitor, and a first electrode of the current control element are connected. The capacitance (including a parasitic capacitance) of the second node is greater than ten times the capacitance (including a parasitic capacitance) of the first node. The capacitance does not affect the first node; thus, a boosting effect is large and charge retention characteristics are favorable.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 20, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yasuhiko Takemura
  • Patent number: 8890571
    Abstract: A method and apparatus for aligning an input signal to a clock signal in an integrated circuit are disclosed. The method includes receiving an input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventor: John G. O'Dwyer
  • Patent number: 8890600
    Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Cypress Semicondductor Corporation
    Inventors: Timothy J. Williams, Harold Kutz, David G. Wright, Eashwar Thiagarajan, Warren S. Snyder, Mark E. Hastings
  • Patent number: 8884650
    Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Takahito Miyazaki
  • Patent number: 8884647
    Abstract: An integrated circuit wherein all elements such as a chip area, a cost, a function to change a logic, an operating frequency, flexibility, a throughput and electric power consumption can be improved; and a reconfigurable processor wherein a function of an instruction can be changed, are provided. A high-density logic reconfigurable leaf cell is defined. The integrated circuit is characterized in that: a logic reconfigurable leaf cell module, which is integrated with high density by arranging a plurality of leaf cells regularly to minimize the connection channel area for a signal between the leaf cells, and the reconfigurable processor, which can change the function of an instruction set by inserting the logic reconfigurable leaf cell module into a data path of an instruction execution process circuit, are integrated.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 11, 2014
    Assignee: Denso Corporation
    Inventor: Tomoyasu Itoh
  • Patent number: 8886696
    Abstract: Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: November 11, 2014
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 8878567
    Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 4, 2014
    Assignee: Altera Corporation
    Inventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
  • Patent number: 8878566
    Abstract: A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmabl
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: November 4, 2014
    Assignee: NEC Corporation
    Inventor: Shogo Nakaya
  • Patent number: 8872543
    Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: October 28, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Pin Lin, Chih-He Lin, Shyh-Shyuan Sheu, Hsin-Chi Lai
  • Publication number: 20140312932
    Abstract: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is changed from a first potential into a second potential lower than the first potential, the logic element changes the potential of a first terminal of the first transistor from a third potential lower than the second potential into the first potential after the logic element changes the potential of the first terminal of the first transistor from the second potential into the third potential. The semiconductor element has a function of making a second terminal of the first transistor floating. The first transistor includes a channel formation region in an oxide semiconductor film.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 23, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki IKEDA
  • Patent number: 8860457
    Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Hari Rao, Sami Khawam, Ioannis Nousias, Raghavan Thirumala
  • Patent number: 8856712
    Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 7, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Srikanth Bojja, Bhavin Odedara
  • Patent number: 8854080
    Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Irfan Rahim
  • Patent number: 8854081
    Abstract: Apparatuses and methods of signal-flow aware supply routing are described. A programmable routing system is configured to route supply signals from a supply generator circuit to one or more functional blocks based on signal channels of the functional blocks.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 7, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold M. Kutz, Hans Klein