Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/47)
  • Patent number: 8072238
    Abstract: A high efficiency PLD architecture having logic elements that can be selectively combined to perform higher order logic functions than can be performed alone by a single logic element. The programmable logic device includes a logic block having a first logic element. The first logic element includes a first pair of sub-function generators and is capable of implementing logic functions of a first order. The logic block also includes a second logic element having a second pair of sub-function generators. A programmable sharing circuitry is also included in the logic block. The programmable sharing circuitry selectively couples the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order. The second order is higher than the first order.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: December 6, 2011
    Assignee: Altera Corporation
    Inventor: Michael D. Hutton
  • Patent number: 8072237
    Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: December 6, 2011
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Andy L. Lee
  • Patent number: 8067959
    Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: November 29, 2011
    Assignee: Actel Corporation
    Inventors: William C. Plants, Suhail Zain, Joel Landry, Gregory W. Bakker, Tomek P. Jasinoski
  • Patent number: 8063661
    Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: November 22, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Takashi Ishihara, Minoru Yamagami, Hisayuki Nagamine
  • Patent number: 8063657
    Abstract: A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 22, 2011
    Assignee: D-Wave Systems Inc.
    Inventor: Geordie Rose
  • Patent number: 8063659
    Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: November 22, 2011
    Assignee: LSI Corporation
    Inventors: Mikhail Grinchuk, Anatoli Bolotov, Sergei B. Gashkov, Lav D. Ivanovic
  • Patent number: 8063660
    Abstract: A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 22, 2011
    Assignee: Xilinx, Inc.
    Inventors: Thomas H. Strader, Roger D. Flateau, Jr., Schuyler E. Shimanek, Wayne E. Wennekamp, Adam Elkins
  • Patent number: 8058897
    Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: November 15, 2011
    Assignee: Xilinx, Inc.
    Inventors: Weiguang Lu, Eric E. Edwards, Paul-Hugo Lamarche, Steven P. Young, Brian C. Gaide, Joe Eddie Leyba, II
  • Patent number: 8054098
    Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 8, 2011
    Assignee: Empire Technology Development LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8049531
    Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: November 1, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Jason Golbus, Colin N. Murphy, Alexander D. Taylor
  • Patent number: 8046727
    Abstract: The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 25, 2011
    Inventor: Neal Solomon
  • Patent number: 8044682
    Abstract: An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 25, 2011
    Assignee: Siliconblue Technologies Corporation
    Inventors: John Birkner, Andrew Ka Lab Chan
  • Patent number: 8040151
    Abstract: A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to select the actively participating pins, enable the desired operation, define the wakeup condition, enter sleep mode, monitor the external signals coupled to the active pins, and exit sleep mode when the wakeup condition is detected.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 18, 2011
    Assignee: Actel Corporation
    Inventor: Theodore Speers
  • Patent number: 8041759
    Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: October 18, 2011
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Robert L. Pelt
  • Publication number: 20110241728
    Abstract: An integrated circuit (‘IC’) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or a distribute signals throughout the IC.
    Type: Application
    Filed: February 11, 2009
    Publication date: October 6, 2011
    Inventors: Jason Redgrave, Martin Voogel, Steven Teig
  • Patent number: 8022724
    Abstract: Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration bitstream is encrypted using values stored in a portion of the configuration memory as a key. The second configuration bitstream is input to the programmable logic IC, and the encrypted portion of the second configuration bitstream is decrypted using the values stored in the portion of the configuration memory. The configuration memory is then programmed with each decrypted portion of the second bitstream.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Xilinx, Inc.
    Inventor: Jesse H. Jenkins, IV
  • Patent number: 8018849
    Abstract: The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: September 13, 2011
    Assignee: Tilera Corporation
    Inventor: David Wentzlaff
  • Patent number: 7999570
    Abstract: In one embodiment, an integrated circuit has an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. An (i?1)-th level of conductors comprising Ii?1 number of conductors selectively couple to the i-th level of conductors comprising Ii number of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((Ii?1×D[i])+Ii×Q) number of switches where each conductor of the Ii?1 number of conductors selectively couples to at least (D[i]+Q) number of conductors of the Ii number of conductors, at least one conductor from each of the D[i] sets of conductors, for Q at least equal to one and D[i] greater than one. The integrated circuit can be used in various electronic devices.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: August 16, 2011
    Assignee: Advantage Logic, Inc.
    Inventors: Benjamin S. Ting, Peter M. Pani
  • Patent number: 7992118
    Abstract: The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two first power supply lines in the same interconnect layer; an actual operation flipflop connected to one of the two first power supply lines and the second power supply line and having a first clock terminal; and a dummy flipflop connected to the other first power supply line and the second power supply line and having a second clock terminal. The dummy flipflop includes: a contact connected to the other first power supply line or the second power supply line; and an interconnect for connecting the second clock terminal with the contact.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 2, 2011
    Assignee: Panasonic Corporation
    Inventors: Takahiro Nagatani, Mitsuhiro Imaizumi
  • Patent number: 7986163
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: July 26, 2011
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7987373
    Abstract: Methods and apparatuses for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design through the use of hardware technologies. According to one embodiment, a hardware sub-design includes a license verification sub-design that is protected from user modification by encryption. In one embodiment, a license is generated based on a trusted host identifier within an external hardware device. In one embodiment, each trusted host identifier is unique, and no two integrated circuits share the same trusted host identifier. In another embodiment, the integrated circuit is a field programmable gate array or an application specific integrated circuit. In one embodiment, a license determines how long the hardware sub-design will operate when the hardware sub-design is implemented within an integrated circuit having a trusted host identifier.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 26, 2011
    Assignee: Synopsys, Inc.
    Inventor: Kenneth S. McElvain
  • Patent number: 7982497
    Abstract: The logical functionality of a non-blocking multiplexer-based network is equivalent to a crossbar network with an ingress stage, a middle stage and an egress stage. Crossbar rows of the crossbar network include both outbound and inbound internal connections between other crossbar rows. The multiplexer-based network has corresponding rows and connections. The multiplexer-based network includes rows with an internal multiplexer for each respective outbound internal connection of a corresponding crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal selected from a set of inputs that includes each input of the respective crossbar row.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 19, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7982496
    Abstract: A bus-based logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multi-bit first and second inputs and a multi-bit output. The logic block includes a multi-bit multiplexer circuit, a multi-bit programmable logic circuit, and a constant generator circuit. The multiplexer circuit has a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output. The programmable logic circuit has a multi-bit first input coupled to the output of the multiplexer circuit, and a multi-bit output. The constant generator circuit has a multi-bit output coupled to the second input of the multiplexer circuit. Each bit of the logic block may be commonly controlled with all other bits of the logic block.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: July 19, 2011
    Assignee: Xilinx, Inc.
    Inventor: Steven P. Young
  • Patent number: 7977974
    Abstract: An integrated circuit device includes a digital power supply regulation circuit, an analog power supply regulation circuit, a control logic circuit, an analog circuit, and a power supply wiring region. A digital power supply line which supplies a digital power supply voltage and an analog power supply line which supplies an analog power supply voltage are provided in the power supply wiring region. The digital power supply regulation circuit, the analog circuit, and the analog power supply regulation circuit are disposed in a first direction with respect to the control logic circuit. The power supply wiring region is formed along a second direction in a region between the control logic circuit and the digital power supply regulation circuit, the analog circuit, and the analog power supply regulation circuit.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Kota Onishi, Takahiro Kamijo
  • Patent number: 7977973
    Abstract: An electronic basic unit for a system on chip comprises a semiconductor substrate and an area on the semiconductor substrate. The area is bounded by a geometric basic shape and the electronic basic unit is formed on the semiconductor substrate and has the form of an integrated circuit. The electronic basic unit further comprises a functional circuit core which determines a function for the electronic basic unit and at least one connecting port at the edges of the geometric basic shape. The at least one connecting port is designed to be coupled to a further connecting port of a further electronic basic unit produced on the semiconductor substrate and being adjacent to the electronic basic unit. The electronic basic unit comprises also a programmable connecting-port controller for controlling data transfers between the electronic basic unit and the further electronic basic unit produced on the semiconductor substrate via the at least one connecting port.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventor: Markus Steiner
  • Patent number: 7973556
    Abstract: A method of operating an integrated circuit having a circuit block configurable by a configuration memory is disclosed. The method includes determining whether to operate the circuit block in a normal operation mode or a low power mode. The configuration memory is loaded with normal operation mode configuration data for the circuit block if the normal operation mode is determined. If the low power mode is determined, the configuration memory is loaded with low power mode configuration data for the circuit block.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 5, 2011
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan
  • Patent number: 7973554
    Abstract: A method of configuring application-specific functional blocks embedded in a user programmable fabric, the user programmable fabric comprising configuration data control means having an input and an output and the application-specific functional blocks comprising configuration memory means having an input and an output. The method comprises the steps of sending configuration data to configure the application-specific functional block to the configuration control means of the user programmable fabric, routing the output of the configuration data control means of the user programmable fabric to the input of the configuration memory means of the application-specific functional blocks, transferring the configuration data to the configuration memory means of the application-specific functional blocks and configuring, using the configuration data, the application-specific functional blocks.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Stuart Parry, Anthony Stansfield
  • Patent number: 7969193
    Abstract: This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N?2) TSVs to act as dummy loadings. The TSV and (N?2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N?2) TSVs.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: June 28, 2011
    Assignee: National Tsing Hua University
    Inventors: Wei-Cheng Wu, Yen-Huei Chen, Meng-Fan Chang
  • Patent number: 7969185
    Abstract: A logical circuit device comprises a plurality of logical blocks including reconfigurable logical configurations and a network including reconfigurable connections among the plurality of logical blocks, wherein at least one of the plurality of logical blocks comprises a basic logical operation element. The basic logical operation element receives a first data signal and a first validity indication signal that becomes an asserted state when the first data signal is valid, outputs a second data signal generated by a first logical operation based on the first data signal and a second validity indication signal that becomes an asserted state when the second data signal is valid, and sets the second data signal to the asserted state in response to the asserted state of the first validity indication signal.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toshio Ogawa
  • Patent number: 7969187
    Abstract: A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: June 28, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen A. Neuendorffer, Paul M. Hartke, Paul R. Schumacher
  • Patent number: 7971172
    Abstract: Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: June 28, 2011
    Assignee: Tabula, Inc.
    Inventors: Daniel J. Pugh, Andrew Caldwell
  • Publication number: 20110148463
    Abstract: A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 23, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kiyoshi Kato, Jun Koyama
  • Patent number: 7965102
    Abstract: A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: June 21, 2011
    Assignee: Xilinx, Inc.
    Inventors: Trevor J. Bauer, Steven P. Young
  • Patent number: 7961004
    Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: June 14, 2011
    Assignee: Sicronic Remote KG, LLC
    Inventors: Deboleena Minz, Kailash Digari
  • Patent number: 7956671
    Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Tom C. Lee, Junjun Li, Robert J. Gauthier, Jr., Christopher S. Putnam, Souvick Mitra
  • Patent number: 7948265
    Abstract: Circuits for implementing logic replication in self-timed integrated circuits are provided. An exemplary circuit includes first and second copies of a replicated circuit, an input circuit, an output circuit, and a pipelined routing path. The first and second copies each have a self-timed input and a self-timed output. The input circuit provides a self-timed input signal alternately to the self-timed inputs of the first and second copies. The output circuit receives the self-timed output from the first copy and the self-timed output from the second copy, and outputs a selected one of the self-timed outputs based on a value of a self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit. The number of pipeline stages in the pipelined routing path can be different from, e.g., less than, the number of stages in both the first and second copies.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: May 24, 2011
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Brian C. Gaide
  • Patent number: 7949971
    Abstract: The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alberto Garcia Ortiz, Cedric Lichtenau, Norman J. Rohrer
  • Patent number: 7944236
    Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 17, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
  • Patent number: 7944234
    Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kirsten S. Lunzer, Jeffrey J. Rooney
  • Patent number: 7941689
    Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charlie Chornglii Hwang, Jose Correia Neves, Phillip John Restle
  • Patent number: 7932746
    Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: April 26, 2011
    Assignee: Achronix Semiconductor Corporation
    Inventors: Raymond Nijssen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake
  • Patent number: 7933277
    Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: April 26, 2011
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Robert D. Turney
  • Patent number: 7932743
    Abstract: A programmable integrated circuit performs an initial partial configuration of the programmable integrated circuit in response to receiving an activation signal. In this way, the programmable integrated circuit enables an initial functionality of the programmable integrated circuit. The programmable integrated circuit then performs a subsequent partial configuration of the programmable integrated circuit for enabling additional functionality of the programmable integrated circuit. In some embodiments, the programmable integrated circuit receives an input signal indicating a stimulus in an environment of the programmable integrated circuit and determines based on the input signal whether to perform the subsequent partial configuration of the programmable integrated circuit or generate a power down signal for powering down the programmable integrated circuit without performing the subsequent partial configuration.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: April 26, 2011
    Assignee: Xilinx, Inc.
    Inventors: Rodney Stewart, Michael Huebner, Juan J. Noguera Serra, Robert P. Esser, Jurgen Becker, Oliver Sander, Matthias Traub, Joachim H. Meyer
  • Patent number: 7928764
    Abstract: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 19, 2011
    Assignee: Agate Logic (Beijing), Inc.
    Inventors: John Jun Yu, Fungfung Lee, Wen Zhou
  • Patent number: 7930658
    Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 19, 2011
    Assignee: Ricoh Company, Ltd.
    Inventor: Keiichi Yoshioka
  • Patent number: 7924053
    Abstract: A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 12, 2011
    Assignee: Actel Corporation
    Inventors: Sinan Kaptanoglu, Wenyi Feng
  • Patent number: 7923755
    Abstract: In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Emi Mizushino, Hidetoshi Nishimura, Junichi Yano
  • Patent number: 7924845
    Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 12, 2011
    Assignee: Mentor Graphics Corporation
    Inventors: Philippe Diehl, Marc Vieillot, Cyril Quennesson, Gilles Laurent, Frederic Reblewski
  • Patent number: 7919977
    Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 5, 2011
    Assignee: Actel Corporation
    Inventors: Jonathan W. Greene, John McCollum, Volker Hecht
  • Patent number: 7919980
    Abstract: A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 5, 2011
    Assignee: NEC Corporation
    Inventor: Shogo Nakaya