Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/47)
  • Patent number: 8307318
    Abstract: A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Kim, Won-Il Bae
  • Patent number: 8302057
    Abstract: A standard cell library is used in design of a semiconductor integrated circuit. A driving force sequence of cells for a single function is in the form of geometric progression with a geometric ratio of the “pth root of 2,” where p is a natural number of 2 or more. A transistor in an output signal driving section of each of the cell is laid out using only layout devices which are limited to p types of sizes. Even if p is small, the driving force sequence can be formed in geometric progression with an extremely low increasing rate. At the same time, sizes of layout devices are discrete and limited, thereby easily securing accuracy of a performance model of a cell. As a result, the standard cell library allows a high-performance circuit to be designed in a highly reliable model.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventor: Shunji Saika
  • Patent number: 8294488
    Abstract: An integrated circuit may include a plurality of sub bit line groups, each sub bit line group coupled to a different main bit line by a corresponding access device; and a plurality of programmable impedance elements arranged into element groups, each element group being coupled to a corresponding each sub bit line.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 23, 2012
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer, John Dinh
  • Patent number: 8291364
    Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 16, 2012
    Assignee: MIPS Technologies, Inc.
    Inventors: Avishek Panigrahi, Soumya Banerjee, Thomas Stephen Chanak, Jr.
  • Patent number: 8289051
    Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Mark F. Turner, Jeff S. Brown, Paul Dorweiler
  • Patent number: 8274306
    Abstract: A physically unclonable function (PUF) device, with corresponding method, is provided for characterizing an integrated circuit. The PUF device includes a digital clock manager (DCM), a Butterfly circuit incorporated within the integrated circuit, and a shift register. The DCM receives a clock input signal (CLK) and imposes a temporal offset to produce a phase-shift signal (PS). The Butterfly circuit receives a first excite signal as said CLK and a second excite signal as said PS. In response, the Butterfly circuit produces an output that shifts state in response to a non-concurrent change in the CLK and PS. The shift register increments a shift count in response to the output.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 25, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Joseph P. Garcia
  • Patent number: 8248102
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 21, 2012
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Herman Schmit, Steven Teig, Brad L. Hutchings, Randy R. Huang
  • Patent number: 8248101
    Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: August 21, 2012
    Assignee: Tabula, Inc.
    Inventors: Martin Voogel, Jason Redgrave, Trevis Chandler
  • Patent number: 8248100
    Abstract: A method and system for providing a logic device are described. The logic device includes a plurality of magnetic input/channel regions, at least one magnetic sensor region, and at least one sensor coupled with the at least one magnetic sensor region. Each of the magnetic input/channel regions is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that at least one domain wall resides in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to at least a portion of the magnetic input regions.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: August 21, 2012
    Assignee: Grandis, Inc.
    Inventors: Dmytro Apalkov, David Druist
  • Patent number: 8242806
    Abstract: Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: August 14, 2012
    Assignee: Altera Corporation
    Inventors: David Cashman, David Lewis, Lu Zhou
  • Patent number: 8242807
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 14, 2012
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 8237470
    Abstract: A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: August 7, 2012
    Assignee: MStar Semiconductor, Inc.
    Inventors: Hsian-Feng Liu, Eer-Wen Tyan
  • Patent number: 8237465
    Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 7, 2012
    Assignee: Altera Corporation
    Inventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
  • Publication number: 20120194216
    Abstract: A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.
    Type: Application
    Filed: October 13, 2010
    Publication date: August 2, 2012
    Inventors: Zvi Or-Bach, Ze'ev Wurman
  • Patent number: 8222923
    Abstract: A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: July 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Schuyler E. Shimanek, Wayne E. Wennekamp, Joe E. Leyba, Adam Elkins, Thomas H. Strader, Chidamber R. Kulkarni, Mikhail A. Wolf, Steven E. McNeil
  • Patent number: 8217700
    Abstract: In one example, a chip includes integrated components configured to operate in the digital domain and the analog domain. An I/O pad located on the chip is configured to provide an external device access to the integrated components. A multifunction I/O interface cell between the I/O pad and the integrated components is configured to selectively connect different combinations of the components to the same I/O pad at different times. The multifunction I/O interface cell may include a first switching device connected to ground, a second switching device connected to a reference voltage, an analog input/output buffer, and a digital input/output buffer.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: July 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy Williams, Harold Kutz, Warren Snyder, David G. Wright
  • Patent number: 8212586
    Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: July 3, 2012
    Assignee: Micrel, Inc.
    Inventors: Thomas S Wong, David Naren
  • Patent number: 8214774
    Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 3, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valentina Nardone, Stefania Stucchi, Luca Ciccarelli, Lorenzo Calí
  • Patent number: 8201129
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 8198915
    Abstract: One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: June 12, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8191033
    Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Marvell International Ltd.
    Inventor: Thomas Page Bruch
  • Patent number: 8191025
    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 29, 2012
    Assignee: Altera Corporation
    Inventors: Michael Chan, Paul Leventis, David Lewis, Ketan Zaveri, Hyun Mo Yi, Chris Lane
  • Publication number: 20120119782
    Abstract: A metal programmable logic unit of a semiconductor device is disclosed. The programmable logic unit comprises: an interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plurality of selectable interconnect geometries, each selectable geometry coupling a said first fixed interconnect to a said second fixed interconnect; and a programmable logic block comprising a plurality of multiplexers, each multiplexer having a plurality of regular inputs, wherein each said regular input is selectively coupled to one of a zero state, a one state, a first input state, and the compliment of the first input state; and a programmable multiplexer having a plurality of regular inputs, wherein each said regular inputs is selectively coupled to one of a zero state, a one state, and one or more input signals; wherein, selecting a subset of the selectable interconnect geometries program the logic block and the multiplexer regular inputs to implement a logic function.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Inventor: Raminda Udaya MADURAWE
  • Patent number: 8174287
    Abstract: A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 8, 2012
    Assignee: Avaya Inc.
    Inventors: Michael German, Michel Ivgi, Roee Elizov, Shlomo Davidson, Yair Khayat
  • Publication number: 20120098569
    Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 26, 2012
    Inventors: Andy L. Lee, Jeffrey T. Watt
  • Patent number: 8165620
    Abstract: Disclosed is the hardware construction of a radio communication apparatus that can meet advanced radio communications. A control bus for transferring control signals between a main processor and components is separated from a data bus for transferring transmission/receive signals between processor units including sub-processors and an external interface. The sub-processors constitute the processor units, and a software defined radio of the present invention may include plural processor units. The processor units are connected by a dedicated interunit interface. The processor units may include multiple sub-processors, which are connected serially through an interprocessor interface.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: April 24, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiko Tsunehara, Hirotake Ishii
  • Patent number: 8159264
    Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: April 17, 2012
    Assignee: Tabula, Inc.
    Inventor: Jason Redgrave
  • Patent number: 8159268
    Abstract: Interconnect structure comprising buffers for a semiconductor device is disclosed.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 17, 2012
    Inventor: Raminda Udaya Madurawe
  • Patent number: 8159266
    Abstract: A metal programmable semiconductor device is disclosed.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 17, 2012
    Inventor: Raminda Udaya Madurawe
  • Patent number: 8161435
    Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: April 17, 2012
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul
  • Patent number: 8151237
    Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 3, 2012
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Patent number: 8143913
    Abstract: A semiconductor integrated circuit judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit, when the power unit is performing the charge operation, the semiconductor integrated circuit determines a logic block that needs to be operated for the execution of a target process, as an operation block whose operation is to be started, and, determines, in the rest of the logic blocks, a logic block having a termination rate whose value is larger than a value of the minimum termination rate, as the operation block whose operation is to be started, the value of the termination rate being larger by more than a predetermined value.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventor: Takahiro Ichinomiya
  • Patent number: 8138797
    Abstract: Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Altera Corporation
    Inventors: Jun Liu, Albert Ratnakumar, Mark T. Chan, Irfan Rahim
  • Patent number: 8138787
    Abstract: A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
    Type: Grant
    Filed: July 13, 2008
    Date of Patent: March 20, 2012
    Assignee: Altera Corporation
    Inventors: Guu Lin, Yen-Fu Lin, Stephanie T. Tran, Pooyan Khoshkhoo
  • Patent number: 8138796
    Abstract: A serial configuration interface (SCI) used to configure a device is disclosed. A device that support SCI includes a first connector configured to receive a first signal and a second connector configured to receive a second signal. In a configuration mode, the first signal serially selects each of a set of one or more configurable options, and the second signal facilitates selection of a desired setting of a selected configurable option. The device further includes control logic configured to determine when configuration of the device is complete and in response output the received first signal via a third connector of the device.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: March 20, 2012
    Assignee: Silego Technology, Inc.
    Inventor: Thomas D. Brumett, Jr.
  • Patent number: 8138792
    Abstract: A gate drive circuit includes a shift register, a clock wiring and a start wiring. The shift register includes a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals. The clock wiring is extended along the first direction. The clock wiring is electrically connected to a plurality of clock connecting wirings extended in a second direction crossing the first direction to deliver a clock signal to the stages. The start wiring includes the first wiring extended along the first direction and a second wiring connected to the first wiring and extended in the first direction to cross with the clock connecting wirings so as to deliver a vertical start signal to a first stage. Therefore, a structure of a signal wiring delivering a vertical start signal is changed, thereby protecting the gate drive circuit from static electricity.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Woong Chang, Kweon-Sam Hong
  • Patent number: 8138788
    Abstract: There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing blocks. Each processing block (13) includes a logic operation unit (21) whose logic is determined by configuration data (17) and a storage unit (40) for storing processing results of the logic operation unit. Each storage unit (40) includes a plurality of storage elements (31r), input means (32) for selecting one of the plurality of storage elements (31r) based on the configuration data (17) to store the output of the logic operation unit (21), and output means (33) for connecting the plurality of storage elements (31r) to the routing matrix (15).
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 20, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Hiroki Honda
  • Patent number: 8136071
    Abstract: The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory components. The integrated circuit components may be on tiles of layers of the 3D IC.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 13, 2012
    Inventor: Neal Solomon
  • Patent number: 8125248
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 28, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Patent number: 8115530
    Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 14, 2012
    Assignee: Altera Corporation
    Inventors: David Lewis, David Cashman, Jeffrey Christopher Chromczak
  • Patent number: 8115511
    Abstract: A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: February 14, 2012
    Assignee: MonolithIC 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 8106683
    Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: January 31, 2012
    Assignee: Achronix Semiconductor Corporation
    Inventors: Raymond Nijssen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake
  • Patent number: 8106682
    Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 31, 2012
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 8098081
    Abstract: A method is implemented for generating a non-blocking routing network design from a crossbar switch-based network design. The non-blocking routing network design includes connections to logic blocks of a programmable integrated circuit. A programmed processor is used to determine, for each row of the crossbar switch-based network design, switches in the row that provide switching functions for logically equivalent external connections, the external connections being one of external inputs and external outputs. The identified switches are removed from the crossbar switched-based network design. Information about the identified switches and the logically equivalent external connections is then stored for access by a placement module associated with the programmable integrated circuit.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 17, 2012
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 8098080
    Abstract: An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazutami Arimoto
  • Patent number: 8098082
    Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: January 17, 2012
    Assignee: Altera Corporation
    Inventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
  • Patent number: 8099704
    Abstract: Methods and systems to improve performance in an Integrated Circuit (IC) are presented. The method includes performing a timing analysis for a circuit design of an IC. The modules in the circuit design use a standard voltage bias by default. In one embodiment, the timing analysis is performed by a circuit design tool. The method then identifies a critical path in the timing analysis, where a signal propagating through the critical path does not meet timing requirements for the circuit design. The method then selects a module of the IC in the critical path to apply a high speed voltage bias to the body of transistors in the module, resulting in a smaller propagation delay thorough the selected module than if the standard voltage bias were applied to the selected module, thus allowing the circuit design to meet the timing requirements.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: January 17, 2012
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 8098079
    Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Oracle America, Inc.
    Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
  • Patent number: 8089300
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: January 3, 2012
    Assignee: Tabula, Inc.
    Inventor: Jason Redgrave
  • Patent number: 8072240
    Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: December 6, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Behnam Malekkhosravi, Daniel J. Woodard, David Ian West