Abstract: A method, apparatus, and system for determining or observing internal state information in a chip.

Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

Abstract: An electronic device having a current switch type driver is provided. The current switch type driver includes a differential circuit that supplies a current to a transmission channel according to a signal. In the electronic device, a signal wire that transmits the signal to the differential circuit has a transmission channel structure.

Abstract: A method of routing input signals in a programmable logic device (PLD) is disclosed. In a PLD having a PLD domain and a vector domain, input signals from the PLD domain are typically routed to the vector domain through an interface. The interface, however, often comprises a limited number of conductors and restricts the amount of data that can be directly transmitted to the vector domain. The disclosed method may be utilized to design an input switching unit that may use PLD-domain resources to route the input signals according to the time periods (or states) in which they operate. The input switching unit may comprise one or more multiplexers that are used to route the input signals in a time-multiplexed manner. As a result of the disclosed method, the amount of data that can be transmitted through the interface is maximized.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.

Abstract: An apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level that is independent of the control signal.

Abstract: In a first aspect, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from the integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus. The second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus. The apparatus further includes a logic circuit adapted to combine any debug signals of the first and second buses onto a third bus. An output stage of the apparatus is adapted to selectively output debug signals of the third bus. Numerous other aspects are provided, as are systems and methods.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract: A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located adjacent to an outer edge of the two-by-two array of FPGA tiles. A plurality of boundary scan register chains are located adjacent to an outer perimeter of the two-by-two array of FPGA tiles and the JTAG, Configuration and BIST interfaces. A plurality of RAM blocks are located adjacent to an outer perimeter of the plurality of boundary register scan chains. A plurality of input/output pad rings is located adjacent to an outer perimeter of the plurality of ram blocks.

Abstract: The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of rows and a number of columns. Each row has a left end and a right end, and each column has a top end and a bottom end. Each row comprises a plurality of functional groups with an interface group located at said right end and said left end. Each column comprises a plurality of functional groups with an interface group located at said top end and said bottom end. A primary routing structure is coupled to said functional groups and interface groups and configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive a primary input signal, perform a logic operation, and generate a primary output signal.

Abstract: The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.

Abstract: A low-voltage programmable connector includes two separate paths. Each path includes a buffer and a pair of transmission gates whose control terminals receive the voltages supplied by a memory element associated with that path. If the voltages supplied by the memory elements respectively close the transmission gates in the first path and open those in the second path, signal is transferred from the first terminal to the second terminal of the connector. If the voltages supplied by the memory elements respectively open the transmission gates in the first path and close those in the second path, signal is transferred from the second terminal to the first terminal of the connector. If the voltages supplied by the memory elements open the transmission gates in both the first and second paths, signal transfer between the first and second terminals of the connector is inhibited.

Abstract: A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Abstract: A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

Abstract: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing network. Uniformly distributed layers of routing network lines re used to provide connections. Switching networks provide connectability between the routing network lines. Additional uniformly distributed layers of routing network lines. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.

Abstract: A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: An electronic system is provided. The electronic system includes a logic device and at least one input/output interface coupled to the logic device. The electronic system further includes an input/output (I/O) device with memory coupled to the at least one input/output interface, wherein the memory of the I/O device is mapped as an address space region that is directly readable and writable by a processor.

Abstract: The present invention provides a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations. In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the invention, a protective transistor is provided between a power-source line and a ground line for an input/output circuit, a position between a power-source line and ground line for a circuit block A, a position between a power-source line and a ground line for a circuit block B, and a position between a power-source line and a ground line for an input/output circuit. A PMOS protective transistor is provided between the power-source line for the circuit block A and the power-source line for the circuit block B, and an NMOS protective transistor is provided between the ground lines in an internal-circuit region in the vicinity of a signal line (protective resistor).

Abstract: In a method of data transmission according to one embodiment of the invention, signals on adjacent conductive paths pass through different sequences of inversions and regenerations. In an apparatus according to one embodiment of the invention, two sets of parallel transmission lines include series of inverting and non-inverting buffers having different sequences.

Abstract: A logic circuit module is used for designing a semiconductor integrated circuit using an FPGA (Field Programmable Gate Array) or a short-term gate array. Provided that a seventh input terminal of the logic circuit module is fixed to the power supply, a third multiplexer always selects the output of a second multiplexer, and a signal selected by the second multiplexer is directly output to a second output terminal. Moreover, an AND circuit always outputs an output signal of a first multiplexer to a first output terminal. Thus, fixing the seventh input terminal to the power supply causes respective logics formed from the first multiplexer and the second multiplexer to be separated by the third multiplexer, allowing for independent representation of the logics. Accordingly, the area efficiency of the logic circuit module is improved, resulting in reduction in size of the semiconductor integrated circuit.

Abstract: This invention discloses a cell forming part of a customizable logic array device, the cell including at least first (34) and second multiplexers, each having a select input and an output, at least two inverters (42, 52), each having an input and an output, and electrical connections (26, 54), selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed. The invention additionally discloses a cell forming part of a customizable logic array device, the cell including a pair of identical logic portion located on opposite sides of a driver portion. The driver portion includes at least two drivers, each having an input and an output.

Abstract: A one-time end-user-programmable fuse array circuit suitable for providing a digital input to a programmable analog element such as a DAC. An end-user-specified digital bit pattern is conveyed to a programming circuit, which programs an array of data fuses in accordance with the specified pattern. A validation means indicates whether the states of the data fuses match the specified pattern. The programming circuit blows a “lock” fuse when the data fuses match the specified pattern, which prevents any additional data fuses from being programmed. The specified pattern and the states of the data fuses are multiplexed to a programmable analog element. Initially, the end-user can vary the pattern to achieve a desired result from the programmable element. When the desired result is achieved, the data fuses are blown, the resulting pattern is validated, and the lock fuse is blown—thereby providing a permanent trim signal.

Abstract: An enhanced scan chain architecture includes scan cells capable of holding two sets of state data associated with the functional blocks, or “modules,” of a system (e.g., an integrated circuit, a multi-chip module, a printed circuit board, and the like), thereby rendering state data associated with a module accessible. The scan chains are employed, during normal operation, to manage (e.g., save, restore, swap, etc.) state data during multi-tasking and/or testing. Control logic redirects the input of the chain, or selected portions thereof, to a source of saved state when initiating or restoring a task; and/or redirects the output of the chain, or selected portions thereof, to a storage source when one task is interrupted and/or another task is resumed.

Abstract: An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.

Abstract: An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.

Abstract: A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an output terminal of the first inverter; a second inverter 11 in which an input terminal is connected to a third node T3; a sixth node T6 connected to an output terminal of the second inverter; a third inverter 12 in which an input terminal is connected to a fourth node T4; a first transfer gate 20 in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T4, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate 21 in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T4; and a fifth node T5 connected to an output t

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Abstract: A matrix switch device comprises a semiconductor integrated circuit chip comprising a 2×2 matrix switch having two input terminals and two output terminals and an SPDT switch at a stage subsequent to the 2×2 matrix switch, the SPDT switch having two input terminals and one output terminal, wherein electrical connection is performed between one of the output terminals of the 2×2 matrix switch and one of the input terminals of the SPDT switch, and wherein the two input terminals and the other of said output terminals of the 2×2 matrix switch, and the other input terminal and the output terminal of the SPDT switch are led out of the semiconductor integrated circuit chip.

Abstract: A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

Abstract: A circuit is provided with a programmable switching matrix incorporating at least one antifuse to selectively route signal paths. The selective routing of signal paths may be used for example, to internally reroute contact pin assignments on semiconductor chips to operate in a plurality of different socket layouts, or to selectively enable or disable features or controls of a circuit. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked therewith.

Abstract: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block.

Abstract: The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.

Abstract: A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of the external terminals of a package is the same as the arrangement of the external terminals of the FPGA. The test terminal corresponds to the data program terminal of the FPGA. When the FPGA is displaced with a gate array, the data program terminal of the FPGA becomes unnecessary and is used as a control terminal for the boundary scan circuit. The position of the test terminal is fixed, thereby to achieve a facilitated, automated and standardized design.

Abstract: A hybrid integrated circuit in which the specification can quickly be modified and adjusted without preparing a new mask and without compromising the performance of the hybrid integrated circuit. The hybrid integrated circuit includes a common substrate on which an electrode pattern is formed; a first monolithic semiconductor chip designed as an ASIC; and a second monolithic semiconductor chip designed as an FPGA.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. The architecture disclosed uses a mixture of hardwired and programmable connections for interconnecting the FPGAs. A hardwired connection is a direct connection between a pair of FPGA I/O pins. A programmable connection refers to the scheme in which pair of FPGA I/O pins are connected using an programmable interconnect device. In the architecture disclosed, the I/O pins in each FPGA are divided into two groups: hardwired connections and programmable connections. The pins in the first group connect to other FPGAs and the pins in the second group connect to FPIDs. The FPGAs and FPIDs are interconnected using a partial crossbar architecture.