Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Abstract: Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.

Abstract: Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

Abstract: A memory element structure in a programmable logic device (PLD) reduces power consumption by placing the memory element in a power save mode when the memory element is unused in a user design implemented in the PLD. An exemplary structure includes a multiplexer driving a memory element. A multiplexer control circuit controls the multiplexer, and also drives a clock control circuit for the memory element. When the memory element is used by a user design implemented in the PLD, one of the data inputs is selected to drive the memory element. The controlled functions occur normally in the memory element. When the memory element is not used by the user design, none of the data inputs is selected, an input control signal is intercepted by the clock control circuit, and the controlled functions do not occur in the memory element, reducing the power consumption of the unused memory element.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract: Techniques are provided for implementing freeze logic on programmable logic blocks. The output signal of a register in each programmable logic block is driven to a predefined state in response to a freeze signal. The freeze signal also causes a multiplexer in each programmable logic block to select the output signal of the register. The multiplexer drives an output signal of the programmable logic block to a predefined state to eliminate contention between circuit elements. The freeze logic requires a small amount of area in each programmable logic block.

Abstract: Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

Abstract: Bidirectional register segmented data busing and addressing for such busing is described. A segmented databus includes data register segments coupled to one another via respective databus segments. Bidirectional drivers are coupled between the data register segments and the databus segments associated therewith. The bidirectional drivers are configurable for driving information along the segmented databus, wherein the databus segments are for both read and write busing.

Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.

Abstract: A crossbar switch (50) is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules (40), the crossbar switch (50) providing communication links between the modules (40). The modules (40) and crossbar switch (50) can be easily updated in a partial reconfiguration process changing only portions of modules (40) and the crossbar switch (50) while other portions remain active. The crossbar switch (50) uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch (50) can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.

Abstract: Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for reconfigurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency. The reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.

Abstract: A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together.

Abstract: A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.

Abstract: Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.

Abstract: A programmable logic block provides fast interconnect paths between memory element output terminals and the input terminals of carry multiplexers in the same logic block. An integrated circuit includes an interconnect structure, a function generator, a carry chain multiplexer coupled to an output terminal of the function generator, and a memory element programmably coupled to the output terminal of the function generator. An output signal from the memory element can traverse the interconnect structure to reach an input terminal of the carry multiplexer. However, a “fast connect” path is also provided that interconnects the memory element output with an input terminal of the carry multiplexer, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to the input terminals the function generator, and to the input terminals of other function generators and/or carry multiplexers in the same logic block.

Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

Abstract: A merged logic element routing multiplexer circuit includes one or more inputs coupled to the logic element (LE) output, one or more tri-stated circuits coupled to the corresponding one or more inputs, wherein the tri-stated circuits are controlled by a set of programmable select signals, and an output port coupled to the inter logic array block (LAB) routing wire, where the output port is connected to outputs of the tri-stated circuits through a buffer circuit.

Abstract: A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also includes a second path connecting a second series of logic elements in the logic array block, where one or more of the logic elements in the second series are not in the first series.

Abstract: A programmable input structure for a logic block provides the capability of “bouncing” a logic block input signal back to the interconnect structure of the integrated circuit, and/or to other input terminals of the logic block, without disabling other functions in the logic block. A programmable input multiplexer circuit selects one of the available signals from the interconnect structure, and passes the selected interconnect signal to a logic block. The signal can be disabled within the logic block by programming a bounce multiplexer circuit to select a static value (e.g., power high or ground) instead of the selected interconnect signal. Therefore, the selected signal is safely provided to the interconnect structure and/or another input multiplexer circuit, in addition to the logic block input terminal.

Abstract: Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core regions. A performance parameter can be collected from each of the core regions. The performance parameter can be collected with a performance measuring mechanism associated with the core region. The performance parameter can be correlated to the performance requirements of an electronic device portion, and the electronic design portion can be implemented in a core region that has a performance parameter matched to the needs of the electronic design portion. In this way, process variation effects are harnessed by optimizing the implementation of the electronic design in regions of the semiconductor device best suited the needs of each electronic design portion. Therefore, performance/power optimization of the semiconductor device can be realized.

Abstract: A method of forming a field programmable gate array architecture having a plurality of input/output pads comprising: providing a plurality of logic clusters; providing a plurality of input/output clusters; providing a plurality of input/output buffers; providing a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; providing an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks, wherein the input/output block controller comprises a dedicated FIFO flag logic block and an input/output FIFO block controller cluster; and providing a routing interconnect architecture programmably coupling the logic clusters, the input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/out

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.

Abstract: A programmable input structure for a programmable logic circuit provides the capability of “fanning out” a selected signal to two or more input terminals of the programmable logic circuit, thereby increasing the routability of the logic block input signals. A logic block for an integrated circuit includes a programmable logic circuit and input multiplexers programmably selecting an input signal to provide to the programmable logic circuit. Also included in the integrated circuit are fan multiplexers that do not drive the programmable logic circuit directly. Instead, the fan multiplexers drive two or more of the input multiplexers that can, optionally, drive other input multiplexers in the same logic block, providing additional selection options among potential input signals. In some embodiments, the fan multiplexers are driven by global and/or regional clock signals. Thus, existing clock distribution structures can be used to provide high fanout input signals to the programmable logic circuit.

Abstract: A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.

Abstract: Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Abstract: An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a center column having circuit elements of different types.

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of memory blocks, and a plurality of continuation routing paths associated with the memory blocks. A plurality of continuation multiplexers, coupled to the continuation routing paths, are adapted to route signals between the memory blocks, between the logic blocks, and/or between the memory blocks and the logic blocks.

Abstract: A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30?). This provides for a reduction in memory area of the reconfigurable processing unit (1).

Abstract: A programmable logic structure is disclosed that has a set of dedicated lines which extend internally throughout different dedicated logic cells within a logic and routing block (LRB), extend from a previous logic routing block to the present logic and routing block, or extend from the present logic and routing block to the next logic and routing block. One set of dedicated lines from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.

Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

Abstract: The present invention relates to electronic circuits that retain identical functionality and performance under RAM and hard-wire ROM fabrication options. An integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises a hard-wired circuit in lieu of said user configurable circuit. Such a programmable to hard-wire conversion provides a significant IC cost reduction at minimal NRE cost and improved reliability.

Abstract: The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output terminals (31, 32, 3i?1, 3i, 3n?1, 3n) adapted to deliver a binary identifying code (B1, B2, Bi?1, Bi, Bn?1, Bn), first electrical paths P1, P2, Pi, Pn), individually connecting said input terminal to each output terminal, and means (4, 51, 52, 5i, 5n) for simultaneously integrating the binary states present in output of the electrical paths, each path inputting a delay sensitive to technological dispersions and/or of the integrated circuit fabrication method.

Abstract: Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.

Abstract: A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Abstract: A general-purpose logic cell used in a general-purpose logic cell array for a logic circuit, includes a plurality of kinds of logic circuit elements, each of which has a plurality of terminals with no connection. The plurality of kinds of logic circuit elements includes a flip-flop and a first inverter set. In this case, each of first inverters of the first inverter set is possible to be connected with an input of the flip-flop in parallel or as one of a series connection of at least two of the first inverters. Also, each first inverter is possible to be connected with an output of the flip-flop in parallel or as one of a series connection of at least two of the first inverters.

Abstract: An apparatus and method adapted to use one-time programming (OTP) devices for multiple-time programming is disclosed. The apparatus includes a selecting device, a first adjusting OTP device, a second adjusting OTP device and a judging device. The judging device outputs a selecting signal according to whether the second adjusting OTP element is programmed. According to the selecting signal, the selecting device selects and outputs either the first OTP signal outputted from the first adjusting OTP device or the second OTP signal outputted from the second adjusting OTP device. By using this apparatus and method, the present invention serves multiple-time programming function without the high costs of manufacturing multiple-time programming devices.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while the second connection scheme specifies a second set of connections between the second node and a set of nodes in the array. The two nodes cannot connect to any nodes on the boundary of the array with any connection that is specified in any connection scheme.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.