Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: A semiconductor storing apparatus capable of performing continuous readout between multiple chips in high speed is provided. A NAND-type flash memory includes the stacked multiple chips. Each of the chips includes: a readout part performing the continuous readout; an output buffer part outputting data readout from the readout part to input/output bus synchronously with a clock signal; and a final page detecting part detecting if readout pages are the final pages of the chips. The output buffer part responds to a detecting result of the final pages under a condition of performing the continuous readout between the chips. After outputting the data of the final pages through a first output buffer with a large driving capability, outputs or holds the data of the final pages through a second output buffer with a little driving capability.

Abstract: Systems and methods for power management for Peripheral Component Interconnect express (PCIE) devices allow PCIE termini to enter advanced low-power states while a PCIE link is idle. These advanced low-power states may include scaling a clock frequency up through a complete shutdown of power rails and clocks within the PCIE terminus. Additionally, use of a wakeup signal such as a clock request (CLKREQ or CLKREQ #) signal may allow the terminus to wake relatively quickly and resume operation so as to avoid degradation of the user experience or loss of data.

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

Abstract: A method, non-transitory computer readable medium, and circuit for wide range voltage translation using monostable multi-vibrator feedback are disclosed. The circuit includes a bias generation segment and a voltage translator to shift a voltage level of a signal from a first voltage domain of a digital system to a second voltage domain of the digital system. The bias generation segment is configured to detect a voltage range of the second voltage domain and to configure the voltage translator responsive to the voltage range. The voltage translator is configured to directly shift the voltage level of the signal to the second voltage domain. The second voltage domain has voltage levels that are higher than a maximum voltage that can be tolerated by transistors in the digital system.

Abstract: A voltage driver is provided that includes a driver circuit, comprising (i) first positive channel transistor devices (PCTDs) coupled in series between a reference node and an output node; and (ii) first negative channel transistor devices (NCTDs) coupled in series between the output node and an electrical ground node. The voltage driver further includes a speed-up circuit comprising: (i) second NCTDs coupled to the first PCTDs, configured to discharge gate-source capacitances of the first PCTDs; and (ii) second PCTDs coupled to the first NCTDs, configured to discharge gate-source capacitances of the first NCTDs. The voltage driver further includes a gate voltage circuit coupled to the driver circuit that includes third NCTDs and third PCTDs to provide respective first and second gate voltages to each of a subset of the first PCTDs and a subset of the first NCTDs.

Abstract: An input buffer circuit may include a first switch that may couple a first voltage source to an output line based on an enable signal, such that the enable signal is configured to cause the input buffer circuit to operate. The input buffer circuit may also include a first set of switches that may couple the first voltage source to the output line based on the enable signal and an input signal, wherein the first switch and the first set of switches may couple the first voltage source to the output line in response to the input signal being greater than an input reference signal. The input buffer circuit may also include a switch that may couple a second voltage source to the output line in response to the input signal being less than the input reference signal.

Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.

Abstract: A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

Abstract: An electronic apparatus includes a controller and a control signal generating circuit. The control signal generating circuit generates a first control signal and a second control signal different from each other for on-off control of two loads on the basis of a state of one three-state port of the controller.

Abstract: Methods and apparatus relating to a programmable scalable voltage translator are described. In one embodiment, logic translates an input voltage level into a plurality of output voltage levels during a low power consumption state of a device. Other embodiments are also disclosed and claimed.

Abstract: A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Abstract: An ESD protection system for an internal circuit is disclosed. The ESD protection system comprises an ESD clamping device connected between a pad and a ground of a first domain); a pre-driver having an output coupled to a gate of the ESD clamping device); an ESD control circuit connected between the pre-driver and the internal circuit; and a transient detection unit coupled to the ESD control circuit, configured to detect an ESD transient from the pad of the first domain. The transient detection unit outputs an first signal to the control circuit upon detection of an ESD transient. In response, the control circuit causes the pre-driver to output a high-impedance state at the gate of the ESD clamping device, thereby floating the gate thereof.

Abstract: A hybrid input/output pad driver includes an input node in a first voltage supply domain coupled to a p-device driver in the second voltage supply domain and an n-device driver in the second voltage domain. A p-channel pullup transistor is coupled between a voltage potential in a third voltage domain and an input/output pad. Its gate is coupled to the output of the p-device driver. An n-channel pulldown transistor is coupled between ground and the input/output pad. Its gate is coupled to the output of the n-device driver. An n-channel pullup transistor has a source coupled to the input/output pad, a drain coupled to the voltage potential in the third voltage supply domain. An inverter in the second voltage supply domain is programmably connectable between the output of the p-driver circuit and the gate of the n-channel pullup transistor.

Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.

Abstract: Methods, devices and systems are disclosed where to generate a pulse a data line is actively driven to a first voltage followed by actively driving the data line to a second voltage.

Abstract: An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

Abstract: In a charging system for portable electronic equipment, providing the charging current is automatically restarted even in the case where an amount of charging current taken into the portable electronic equipment exceeds charging current providing capacity of a USB battery charger and the USB battery charger stops providing the charging current. When a voltage at a VBUS terminal is lower than a first predetermined voltage, a CPU assumes that the USB battery charger has stopped providing the charging current and turns off a first switching device. And the CPU turns on a second switching device for a predetermined period of time. As a result, the voltage at the VBUS terminal falls to 0.7V or below during the predetermined period of time. In response to the change in the voltage at the VBUS terminal, the USB battery charger restarts providing the charging current to the VBUS terminal.

Abstract: Methods, devices and systems are disclosed where to generate a pulse a data line is actively driven to a first voltage followed by actively driving the data line to a second voltage.

Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.

Abstract: A semiconductor device includes a transistor, a light-emitting element, a first wiring, a driver circuit having a function of controlling the potential of the first wiring, a second wiring, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. One of a source and a drain of the transistor is connected to the light-emitting element. With this structure, voltage applied between the source and the gate of the transistor can be corrected in anticipation of variations in threshold voltage, so that the current supplied to the light-emitting element can be corrected.

Abstract: The present invention relates to a tristate gate (1000, 2000) comprising an output port (1400) and at least two transistors (1200, 1300; 2200, 2300), each having at least a first and a second gate, configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.

Abstract: The present disclosure relates to an Apparatus comprising at least one resistive voltage divider and at least two inverters, wherein the resistive voltage divider is coupled between a first supply potential terminal (VDD) and a second supply potential terminal (VSS), wherein the voltage divider comprises a first resistor, a second resistor, a third resistor and a fourth resistor being serially connected, and wherein a first connection point of the second resistor and the third resistor is connected to an voltage input, and a second connection point of the first resistor and the second resistor is connected to the input side of a first inverter, and a third connection point of the third resistor and the fourth resistor is connected to the input side of a second inverter, wherein the first inverter and the second inverter are configured to provide a first output voltage if a first voltage is applied to the voltage input, and the first inverter and the second inverter are configured to provide a second output vo

Abstract: Disclosed herein is a device that includes first and second logic circuits driving first and second output nodes, respectively. The first logic circuit includes first and second transistors that are coupled in series between the first output node and a power line, in which the first transistor is controlled to change between a conductive state and a non-conductive state and the second transistor is controlled to keep a conductive state. The second gate circuit includes third and fourth transistors that are coupled in series between the second output node and the power line, in which each of the third and fourth transistors is controlled to change between a conductive state and a non-conductive state.

Abstract: A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and non-connection of the input terminal IN and a second supply VSS are provided. The pull-up switching device and the pull-down switching device are operated exclusively on and off in time division to hold and output the state of the input terminal during each operating state from the two output terminals.

Abstract: A repeater circuit. The repeater circuit includes two input circuits, two intermediate circuits, and two output circuits. Responsive to a transition of an input signal from one logic level to another level, one of the input circuits is activated. The corresponding intermediate circuit is activated corresponding to activation one of the input circuits, and in turn, the corresponding output circuit is activated, which then drives an output signal on an output node. After a delay, a feedback signal conveyed via a feedback path deactivates the corresponding intermediate circuit and the corresponding output circuit. After deactivation of the corresponding output circuit, a keeper circuit continues to provide the output signal on the output node. The other one of the two input circuits inhibits activation of the other one of the intermediate circuit responsive to the transition, which results in the other output circuit also being inhibited from activation.

Abstract: A voltage sequence output circuit includes a sequence control circuit and a number of voltage output circuits. The sequence control circuit includes a first NOR gate, and the first NOR gate includes a number of the input terminals. The voltage output circuits each includes an input terminal, an output terminal, and a positively enabled tristate buffer connected between the input terminal and the output terminal thereof. The input terminals of the voltage output circuits is connected to the input terminals of the first NOR gate. If all of input terminals of the voltage output circuits are connected with electronic devices, the positively enabled tristate buffer of the voltage output circuits are enabled. The output terminals of the voltage output circuits sequentially output a voltage.

Abstract: Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.

Abstract: A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.

Abstract: Isolation components such as p-n junction or Schottky diodes are provided at pull-up resistors of each signal line of a Gunning Transceiver Logic (GTL) backplane bus in an electronic system for improved reliability, specifically to prevent momentary termination of the bus to ground when a circuit card incorporating the pull-up resistors is inserted into the system.

Abstract: A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.

Abstract: A driver includes a plurality of first PMOS transistors, a first resistor, a amplifier, a second PMOS transistor and a second resistor. The amplifier herein receives a reference voltage and outputs a regulating voltage. The above-mentioned reference voltage is produced in accordance with a band-gap reference voltage. Since the band-gap reference voltage is unlikely affected by a process variation, thus, the present invention is capable of providing an output current robust from process characteristic and the output current is more reliable to indicate a data signal.

Abstract: Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

Abstract: Three devices such as electric charge-coupled devices are each included in one of three phase impedance circuits composing a 3-phase LC resonance circuit as a device having a capacitive impedance. A driver circuit applies either of a logic level of 0, a high-impedance level or a logic level of 1 to each of nodes Node_A, Node_B and Node_C of the phase impedance circuits so as to result in sequential transitions of a state of resonance among the phase impedance circuits. In an operation to drive the phase impedance circuits, either of the logic level of 0, the high-impedance level and the logic level of 1 is applied to each of the nodes so as to sustain a phase difference of 2?/3 between the phase impedance circuits. In this way, the logical levels and the phases of the logical levels are assigned to the nodes in such a way that the logical levels do not overlap with each other at any timings each corresponding to a point of time.

Abstract: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

Abstract: A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.

Abstract: In normal operation, an internal circuit operates in synchronism with a clock CK, so that switching operation of the output circuit is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit to a three-state control circuit is forcedly set by state control circuits, whereby different test operations are performed on the output circuit.

Abstract: As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control enable signal is set to “L,” the PMOS turns off, thus holding the bi-directional bus in a high-impedance state. By setting the data bus control enable signal in accordance with the specifications of a peripheral device connected thereto, the state of the bi-directional bus can be arbitrarily set when it is inactive.

Abstract: An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined voltage level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined voltage level of the input signal according to a second enable signal and outputs the input signal with the determined voltage level at the output terminal to serve as the output signal.

Abstract: A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

Abstract: An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.

Abstract: Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path.

Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

Abstract: In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.

Abstract: A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the buffer operating efficiency. The technique is implemented to allow for a reduction of power associated with the output buffer pre-driver stage. The methodology employs a power efficiency control circuit that tri-states the output buffer before every transition.

Abstract: An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level.

Abstract: A semiconductor device including a tristate buffer circuit, which includes, on an output stage, at least a first transistor (P1) for pull-up driving and a second transistor (N1) for pull-down driving, in which, when a control signal (EN) is of a value indicating an enable state, an output is set to a high level or to a low level, depending on a data signal, and in which, when the control signal is of a value indicating a disable state, the first and second transistors are turned off to set a high impedance state of the output. The semiconductor device further includes a control unit (120, P6, P7) for performing control for speeding up the transition from the on-state to the off-state of the first transistor (P1) at the time of switching the control signal (EN) from the enable state to the disable state.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.