Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a programmable device. The first P-type FET is coupled between a first power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: An interface circuit includes an input current limiting circuit for limiting a current of an input signal fed from a preceding circuit, thereby outputting the current-limited signal to a following circuit which is constituted using a MES type transistor. The interface circuit also includes a level shifting circuit supplied with a first higher power supply voltage and a lower power supply voltage, for converting a level of the current-limited signal into a logic level of the following circuit which is supplied with a second higher power supply voltage. The interface circuit further includes a level judging circuit connected between the input current limiting circuit and the level shifting circuit, for judging a logic threshold level of the input signal based on a predetermined level reference voltage. By the constitution, it is possible to adapt the interface circuit for connection to the following circuit constituted using MES type transistors.

Abstract: A low-voltage driven semiconductor device is simple to fabricate, operates at high speed, and consumes low power. The semiconductor device is made of first and second MISFETs connected in series. The MISFETs have channels of the same conduction type. If the conduction type is n, the drain and gate of the first MISFET are connected to the high-potential side of a power source. The source and well of the second MISFET are connected to the low-potential side of the power source. The well of the first MISFET and the gate of the second MISFET are connected to a signal input terminal. A voltage applied to ends of the MISFETs and the potential fluctuation range of a signal supplied to the signal input terminal are each set to be lower than a voltage determined by a built-in potential (a forward withstand voltage) of a pn junction between a well of the first MISFET and a diffusion layer of the same. The diffusion layer is one that is adjacent to the second MISFET.