Abstract: A computer-implemented method and system for determining a wiring network in a multi-core processor. The method includes determining, using a layered-and-progressive determination model, a wiring network including wiring path(s) for operably connecting multiple processor cores in the multi-core processor. The method also includes outputting a layout of the determined wiring network for display. The layered-and-progressive determination model is arranged to model the plurality of processor cores as a mesh of nodes arranged in the form of a rectangular array with n rows and m columns. Nested layer(s) are identified from the rectangular array. Each of the nested layers is formed by respective plurality of nodes connected in respective rectangular paths of the same shape but different sizes. A respective rectangular wiring path for each of the nested layer(s) is determined. The respective rectangular wiring paths are of the same shape but different sizes.

Abstract: A voltage regulator circuit is disclosed. The voltage regulator circuit includes a level shifter circuit. The level shifter circuit includes first and second nodes that each switch between a first low voltage and a first high voltage, third and fourth nodes that each switch between a second low voltage and a second high voltage, where the second high voltage is different from the first high voltage. The level shifter circuit also includes a DC path circuit connected between the first and third nodes, and arranged to selectively conduct a current between the first and third nodes.

Abstract: Methods and devices to decrease the power consumption of level shifters in the absence of input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the HIGH or LOW steady state. The disclosed methods further include a delay element used to keep the power consumption low in the case of slow input power supply ramps.

Abstract: A level conversion circuit includes a first pin, a second pin, a target pin, a core module and a switch. A first terminal of the switch is connected to the first pin, a second terminal of the switch is connected to the second pin, and the core module is connected to the target pin, the second pin and a control terminal of the switch respectively. The core module is configured to: when a voltage connected to the target pin is at a first reference high level, control the switch to turn on to transmit a signal with a specified voltage amplitude, and pull the first pin to the first reference high level and the second pin to a second reference high level based on the first reference high level; where the first reference high level is higher than the second reference high level.

Abstract: A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.

Abstract: A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

Abstract: A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

Abstract: A level shifter includes a pre-level shifter and a selector. The selector is coupled to the pre-level shifter. The pre-level shifter shifts an input digital voltage to a first digital voltage and a second digital voltage. The levels of the first digital voltage and the second digital voltage transition sequentially in time when the level of the input digital voltage transitions from one logic to the other. The selector selects and outputs the first digital voltage whose level transitions earlier in time compared to the transition of the level of the second digital voltage.

Abstract: Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.

Abstract: Methods for improving read time performance and energy consumption when reading multiple pages within a memory block by dynamically skipping or accelerating unselected word line discharge cycles are described. In some cases, a controller or one or more control circuits in communication with word lines and bit lines associated with a memory block may detect that a read command or instruction for reading a second page within the memory block has arrived prior to the word line discharge phase associated with reading a first page within the memory block, and in response, the controller may skip the discharge cycle for unselected word lines within the memory block prior to reading the second page and initiate the next page read for the second page after a partial discharge period of time.

Abstract: A semiconductor device capable of level shifting in a negative potential direction using an n-channel transistor is provided. The semiconductor device includes a first source follower, a second source follower, and a comparator. The first source follower is supplied with a second high power supply potential and a low power supply potential; the second source follower is supplied with a first high power supply potential and the low power supply potential; and a digital signal which expresses a high level or a low level using the second high power supply potential or the first high power supply potential is input to the first source follower. Here, the second high power supply potential is a potential higher than the first high power supply potential, and the first high power supply potential is a potential higher than the low power supply potential.

Abstract: An integrated circuit device includes a level shifter circuit with a supply voltage rail to provide a supply voltage, a first pull-up circuit coupled between the supply voltage rail and a first node, a second pull-up circuit coupled between the supply voltage rail and a second node, a first switch including a first terminal coupled to the supply voltage rail, a second terminal coupled to the first node, and a control terminal coupled to the second node, and an inverter including an input terminal coupled to the first node, a voltage supply terminal coupled to the supply voltage, and an output terminal to provide an output voltage from the level shifter circuit.

Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.

Abstract: A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Abstract: An input/output (I/O) level shifter for a subscriber identification module (SIM) interface includes a controller configured to apply a first enable signal to turn ON a first transmitter when the direction of packet flow is from an interface device to a SIM card, and is configured to apply a second enable signal to turn ON a second transmitter when the direction of packet flow is from the SIM card to the interface device. The controller is configured to not apply the first and the second enable signals concurrently. The controller selectively controls the ON/OFF period of the first and the second transmitter to maintain half-duplex communication on the interface I/O line and the SIM I/O line to prevent undesired positive data feedback.

Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.

Abstract: A driving apparatus is provided. A first stage inverter circuit and a second stage inverter circuit respectively generate a first output signal and a second output signal according to a first voltage dividing control signal and a second voltage dividing control signal, wherein the first output signal and the second output signal are respectively output to the second-stage inverter circuit and the first-stage inverter circuit to appropriately control the gate voltages of transistors of pull-up circuit and the pull-down circuit in the first-stage inverter circuit and the second-stage inverter circuit, so that source-drain voltages differences of the transistors can be more evenly distributed.

Abstract: A circuit for translating a voltage of a digital signal from a first voltage level of a first voltage domain to a second voltage level of a second voltage domain is disclosed. The circuit includes a configurable circuit to be coupled between the first voltage domain and the second voltage domain. The configurable circuit includes a plurality of parallel data paths, wherein the configurable circuit is configured to enable only one of the plurality of data paths at a given time. A first path in the plurality of parallel data paths is configured to be enabled when the first voltage level is greater than the second voltage level and a second path in the plurality of parallel data paths is configured to be enabled when the first voltage level is lesser than the second voltage level.

Abstract: Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal into a low-voltage signal. The high voltage input signal is split into a upper portion and a lower portion. The upper portion is coupled to a high input receiver that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

Abstract: The present invention provides a voltage level shifter architecture applicable for positive and negative voltage shifting, in which a shielding circuit is configured to relax the voltage stress of the transistors in the input stage circuit, and a switching circuit is configured to avoid current leakage. In addition, designing the power domain(s) of the n-well P-type transistors in the voltage-level shifter makes the voltage-level shifter area-efficient and power-efficient or design-flexible and application-adaptive.

Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.

Abstract: The present disclosure provides a level shifting circuit which includes a boost subcircuit and a first phase-inverting subcircuit. The boost subcircuit has a first terminal being coupled to an input terminal of the level shifting circuit, a second terminal being coupled to a first high level signal terminal, a third terminal being coupled to a low level signal terminal, a fourth terminal being coupled to a first terminal of the first phase-inverting subcircuit; the first phase-inverting subcircuit has a second terminal being coupled to the first high level signal terminal, a third terminal being coupled to the low level signal terminal, a fourth terminal being coupled to a first output terminal of the level shifting circuit, the first phase-inverting subcircuit is configured to cause the third terminal to be electrically coupled to the fourth terminal when the first terminal thereof receives a high level signal.

Abstract: Methods and apparatus to provide a high-efficiency drive for a floating gate are disclosed. An example apparatus includes a driver including a supply terminal, the driver configured to output a third voltage corresponding to the supply terminal, the driver to drive a gate of a transistor in a power converter; and a second capacitor to be charged using a first discharging current of a first capacitor and discharged at the supply terminal of the driver, the driver to drive the gate of the transistor based on a second discharging current from the second capacitor.

Abstract: A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.

Abstract: A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

Abstract: To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.

Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

Abstract: Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.

Abstract: A signal interface system and a data transmission method thereof are provided. The signal interface system includes a data line, a clock line, a master circuit, and at least one slave circuit. The master circuit has a main data pin coupled to the data line and a main clock pin coupled to the clock line. The at least one slave circuit has a secondary data pin coupled to the data line and a secondary clock pin coupled to the clock line. The master circuit transmits a main control data to the at least one slave circuit through the data line, and transmits an additional control data to the at least one slave circuit through the clock line.

Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Abstract: An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was to received prior to the particular data symbol.

Abstract: A level shifter (100) is presented comprising an input branch (102) and an output branch (104). The input branch comprises a first switch (130), a voltage clamping unit (120) and a controllable current source (110) in series. The output branch (104) comprises a second switch (140) and a third switch (150) in series, the second switch (140) and third switch (150) having opposite polarities. An output (OUT, 160) is provided between the second and the third switch (140, 150). The current source (110) is controlled by an input signal (IN) and the output signal (OUT). The first switch (130) is controlled by the input signal (IN). Switching control terminals (122, 124) of the second and the third switch are connected on either side of the clamping unit (120). This reduces voltage swing of switching control units, thus resulting in fast switching, less power consumption and wider voltage ranges.

Abstract: The present disclosure provides a level shifting unit which includes, for example, a logic control module, an output module, an output control module and a feedback module. The logic control module is connected to a turn-on power supply, a driving power supply, an input signal terminal, and the output module. The feedback module is connected to an enable signal terminal, a signal output terminal, and the output control module. The output control module is connected to the output module and the driving power supply. The output module is connected to the signal output terminal. The feedback module controls to turn on or turn off the output module through the signals outputted from the enable signal terminal and the signal output terminal. If the signals outputted by two level shifting units are short circuited, the feedback module controls the output control module of the level shifting circuit to be disconnected.

Abstract: A highly reliable micromachine, display element, or the like is provided. As a micromachine or a transistor including the micromachine, a transistor including an oxide semiconductor in a semiconductor layer where a channel is formed is used. For example, a transistor including an oxide semiconductor is used as at least one transistor in one or a plurality of transistors driving a micromachine.

Abstract: The present disclosure relates to a current memory circuit for minimizing clock feedthrough, the circuit including: a first memory capacitor implemented as a first conductive type MOS; a second memory capacitor implemented as a second conductive type MOS; and a dummy capacitor for connecting the first memory capacitor and the second memory capacitor to each other, wherein the first memory capacitor and the second memory capacitor are current mirrors. Accordingly, a current memory circuit with a more accurate performance, low power consumption, and an integration capability can be provided.

Abstract: A level shift circuit receives an first input logic signal and a second input logic signal, and generates a first output logic signal and a second output logic signal. The level shift circuit includes a first current mirror module, a second current mirror module, and a latch module. The first current mirror module and the second current mirror module respectively output a first control logic signal having a phase performance following the first input logic signal and a second control logic signal having a phase performance following the second input logic signal. The latch module is coupled to the first current mirror module and the second current mirror module. The latch module receives the first control logic signal and the second control logic signal, and updates correspondingly and stores the output logic signal and the complementary output logic signal.

Abstract: A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.

Abstract: A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.

Abstract: There is provided a semiconductor device including (1) a first power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, (2) a first output section that includes a first output stage switch that is provided between the first power source output terminal and a first voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the first power source output terminal, and (3) a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing a point in time when a signal level of the first signal switches.

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.