Interface (e.g., Current Drive, Level Shift, Etc.) Patents (Class 326/62)
  • Patent number: 10784795
    Abstract: A conversion circuit includes a main device, a voltage control circuit and a trigger circuit. An output terminal of the voltage control circuit is electrically connected to a control terminal of the main device. The voltage control circuit is configured to output a driving signal having a first voltage level to the main device. The trigger circuit comprises an output terminal and a sense terminal. The output terminal of the trigger circuit is electrically connected to the control terminal of the voltage control circuit, and the sense terminal of the trigger circuit is electrically connected to the control terminal of the main device.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 22, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Hsiang Chao, Po-Chin Chuang
  • Patent number: 10784770
    Abstract: A conversion circuit includes a main device, a voltage control switching circuit and a trigger circuit. The trigger circuit includes an output terminal and a sense terminal. The sense terminal is electrically connected to the control terminal of the main device. The voltage control switching circuit includes a first terminal, a second terminal and a control terminal. A first terminal is configured to receive an original signal. A second terminal is connected to a control terminal of the main device, and is configured to transmit a driving signal to drive the main device. A control terminal is connected to the main device and the output terminal. The driving signal has a first voltage level generated by the voltage control switching circuit in response to a voltage level at the control terminal of the voltage control switching circuit.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 22, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Hsiang Chao, Po-Chin Chuang
  • Patent number: 10778219
    Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 15, 2020
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Patent number: 10759287
    Abstract: A battery charger capable of receiving AC power and delivering both AC and DC power to an electric power storage battery in accordance to different embodiments disclosed herein using a rectifier circuit supplying the DC load and absorbing power as a five-level active rectifier with low harmonics on the AC input. In one aspect, the battery charger may have a bidirectional rectifier/inverter converter providing power conversion between a DC source and AC enabling the user to not only charge an electrical vehicle (“EV”) but also convert the energy charged in the EV/battery or solar panel to AC for use.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 1, 2020
    Assignee: OSSIACO INC.
    Inventors: Hani Vahedi, Marc-André Forget, Peter Ibrahim
  • Patent number: 10740275
    Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes logic and a serial data bus interface. The serial data bus interface is to interface with a serial data bus of a print apparatus, and the logic is, in response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, to generate a low voltage condition on the serial data bus and to monitor a duration of a time period.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 11, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen D. Panshin, Scott A. Linn
  • Patent number: 10734882
    Abstract: A conversion circuit includes a main device including a first terminal, a second terminal and a control terminal, and a voltage control switching circuit including a first terminal configured to receive an first driving signal, a second terminal coupled to the control terminal of the main device and configured to transmit a second driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A current passing through the voltage control switching device is controlled in response to a voltage level of the reference terminal.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Hsiang Chao, Po-Chin Chuang
  • Patent number: 10707871
    Abstract: A level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: July 7, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Mohammad Al-Shyoukh
  • Patent number: 10574236
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: February 25, 2020
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Cagla Cakir
  • Patent number: 10535386
    Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 14, 2020
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Rahul Mathur, Abhishek Baradia, Hsin-Yu Chen
  • Patent number: 10528324
    Abstract: Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 7, 2020
    Assignee: Microsemi Storage Solutions, Inc.
    Inventor: Dan Stiurca
  • Patent number: 10505541
    Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Albert Kumar, Ramaprasath Vilangudipitchai, Vasisht Vadi, Paul Penzes
  • Patent number: 10469086
    Abstract: Level-shifter circuits and methods of using the same are provided. A level-shifter circuit includes a latch unit and a level-shifting unit. The latch unit is configured to generate a latch signal for storing a logic state of a first digital signal in a first power supply domain. The level-shifting unit is configured to shift a voltage of the latch signal to output a second digital signal in a second power supply domain. The latch unit and the level-shifting unit are powered by a power supply voltage in the second power supply domain.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 5, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Chia Chi Yang, Jun Tao Guo, Chen Yi Huang
  • Patent number: 10418997
    Abstract: Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 17, 2019
    Assignee: ABLIC INC.
    Inventor: Kaoru Sakaguchi
  • Patent number: 10404251
    Abstract: The technology described herein is generally directed towards a self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor and diode are used with a first inverter coupled to a control signal input terminal, a second inverter coupled to the first inverter, a push-pull circuit comprising a pull-up transistor and a pull-down transistor and a power device comprising a power device transistor with a gate. Control signal input at one state controls the first inverter to a first output state, turns on the pull-down transistor to discharge the gate of the power device transistor, turns off the power device and charges the capacitor through the diode. The control signal input in another state controls the first inverter to a second output state, turns off the pull-down transistor and turns on the pull-up transistor via the capacitor to turn on the power device.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: September 3, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jing Chen, Gaofei Tang
  • Patent number: 10382021
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: August 13, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 10348305
    Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 9, 2019
    Assignee: ABLIC INC.
    Inventors: Hideyuki Sawai, Masakazu Sugiura
  • Patent number: 10348291
    Abstract: A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 9, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Seiichiro Sasaki
  • Patent number: 10298237
    Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 10296034
    Abstract: A negative power supply control circuit which controls a negative voltage regulator circuit based on a positive voltage control signal, the negative power supply control circuit including: a control signal input terminal a negative voltage input terminal; a negative voltage input control signal output terminal; a voltage current conversation circuit; a first current source; and a first clamp circuit, wherein the first clamp circuit clamps a voltage at a first intermediate point between the first clamp circuit and the first current source by limiting a current flowing in the first clamp circuit according to the voltage at the first intermediate point in a period when a current flows in the voltage current conversation circuit, and the negative voltage controls signal is generated based on a voltage or a current in a current path through the voltage current conversation circuit, the first clamp circuit and the first current source.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 21, 2019
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Kohei Sakurai, Yoichi Takano
  • Patent number: 10282278
    Abstract: A system, a method, and a computer program product for visualizing an outcome of dependency checks and resolution of errors in various software applications are disclosed. At least one first configuration setting in a plurality of configuration settings for a software application is selected. At least one first graphical notification identifying an error preventing execution of the first configuration setting and another configuration setting in the plurality of configuration settings are generated and displayed. The first graphical notification is displayed on a user interface adjacent to a graphical location on the user interface associated with another configuration setting. At least one solution to the error is executed based on the at generated first graphical notification. An absence of errors preventing execution of the plurality of configuration settings is determined and the plurality of configuration settings is executed.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 7, 2019
    Assignee: SAP SE
    Inventors: Cora Zimmermann, Jan Loehe, Balazs Rabel, Ning Gao
  • Patent number: 10276638
    Abstract: A data driver and a display device using the same are disclosed. The display device includes a display panel having a display area displaying an image, signal lines including data lines, first power lines, and sensing lines connected to the display panel, and a data driver connected to the signal lines. The data driver includes first channel groups outputting a data signal, second channel groups outputting and sensing a sensing voltage, and third channel groups outputting a high potential voltage. The first channel groups and the third channel groups are defined as a first output unit, and the second channel groups are defined as a second output unit. The second channel groups are successively disposed every M channels, where M is an integer equal to or greater than 2.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 30, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Joonmin Park, Sungjoon Bae
  • Patent number: 10262706
    Abstract: An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Ching-Wen Chen, Chieh-Yao Chuang, Yu-Yen Lin
  • Patent number: 10256820
    Abstract: Various implementations described herein are directed to a circuit for translating an input signal from a source voltage domain to an output signal for a destination voltage domain that is is different than the source voltage domain. The circuit may include a level shifting portion configured to operate with a supply voltage that exceeds a stressing threshold of one or more components within the circuit. The level shifting portion may be configured to generate the output signal for the destination voltage domain based on the input signal and a power management signal. The circuit may include an isolating portion configured to isolate the one or more components from the supply voltage during activation and deactivation of the circuit based on the power management signal.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 9, 2019
    Assignee: ARM Limited
    Inventors: Jean-Claude Duby, Mikael Rien
  • Patent number: 10228712
    Abstract: This document discusses, among other things, a signal receiving circuit, configured to receive an input voltage signal. The signal receiving circuit can comprise an input voltage regulating circuit and a comparing circuit. The input voltage regulating circuit can carry out a waveform pre-regulation for the input voltage signal to obtain a first voltage signal, and the comparing circuit can compare the first voltage signal with a second voltage signal, and output a comparison voltage signal having a pulse width that satisfies a first predetermined condition indicative that the input voltage signal is correctly identifiable. The present document further discusses a signal detecting circuit and a signal receiving method.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zhaohong Li, WeiMing Sun, Lei Huang
  • Patent number: 10217399
    Abstract: The present invention relates to a level shifter including: a first inverter applied with a first voltage and a second voltage of different polarities and operated depending on an input voltage to output a first inverting output signal; a second inverter applied with the first voltage and the second voltage and operated depending on the first inverting output signal to output a second inverting output signal having an opposite polarity to that of the first inverting output signal; a driver applied with a third voltage and a fourth voltage, including a first load transistor having the first inverting output signal as a gate input and a second load transistor having a fifth voltage as the gate input, and outputting an output voltage having an increased level with respect to the input voltage; and a bootstrap capacitor positioned between an output terminal of the second inverter and a gate electrode of the second load transistor to help the fifth voltage to be bootstrapped depending on the second inverting outpu
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 26, 2019
    Assignee: SILICON DISPLAY TECHNOLOGY
    Inventors: Kijoong Kim, Young Man Park, Ji Ho Hur
  • Patent number: 10217393
    Abstract: A display device includes: a display panel including pixels arranged in a matrix shape; and a source driver to apply data voltages to the pixels. The source driver includes: a shift controller to shift a sampling control signal; a latch array to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array to output the data voltages from the digital-to-analog converter array; and a bias controller to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 26, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Ju Young Noh, Jun Hyeok Yang, Kyoung Don Woo
  • Patent number: 10164481
    Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 25, 2018
    Assignee: WiTricity Corporation
    Inventor: Douglas S. Piasecki
  • Patent number: 10128846
    Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yeshwanth Kumar Mallavajula, Wilson Chen, Chiew-Guan Tan
  • Patent number: 10063219
    Abstract: Aspects of the disclosure are directed to a voltage level shifter architecture, including a voltage level shifter with circuitry residing within a footprint; and an internal augmented voltage generator residing within the footprint, wherein the internal augmented voltage generator is coupled to the voltage level shifter to augment a voltage level shift.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Srivastava, Satadru Sarkar, Samarth Vasishtha
  • Patent number: 10014847
    Abstract: A trigger, includes: a first voltage input terminal; a bias voltage input terminal; a first bias transistor having a scaling of N to a first component of an external device; a comparator transistor having a scaling of N to a second component of the external device; a first switch transistor and a second switch transistor; a shunt transistor having a control terminal connected to the first voltage input terminal, a second terminal connected to the second terminal of the second switch transistor, and a first terminal connected to the first terminal of the comparator transistor. The shunt transistor has an enlarging scale of M to the comparator transistor. A voltage output terminal is respectively connected to the second terminal of the first switch transistor, the control terminal of the second switch transistor, and the second terminal of the comparator transistor.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 3, 2018
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 9916166
    Abstract: This invention provides an array-type processing device which can reduce power consumption and can also reduce a processing performance drop caused by switching of configuration information. An array-type processing device, which includes a first domain and a second domain, the device comprises a plurality of processing units which are allocated in the first domain, and each of which includes a plurality of processing elements and a router configured to control connections between the plurality of processing elements, a configuration information supply unit configured to supply configuration information to one or more processing units of the plurality of processing units, the configuration information supply unit being allocated in the second domain, and a power supply control unit configured to control the power supply to the plurality of processing units, the power supply control unit being allocated in the second domain.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: March 13, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Eiji Aizawa
  • Patent number: 9904340
    Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 27, 2018
    Assignee: Nuvoton Technology Corporation
    Inventors: Yung-Chen Chu, Chia-Ching Lu, Ming-Che Hung
  • Patent number: 9857215
    Abstract: An object information acquiring apparatus includes a detector including m-number of probes to which a voltage is supplied and a current/voltage conversion circuit which converts a current into a voltage, a receiver processing electric signals from the probes, and a relay board respectively relaying power distribution lines between the electrical power source and the probes and signal wirings between the receiver and the probe, wherein the relay board receives input of signal wirings and power distribution lines from n-number (m?n) of probes among the m-number of probes, connects the signal wirings from the n-number of probes to the receiver, and connects, to the electrical power source side, the power distribution lines of a number that is fewer than the power distribution lines from the n-number of probes.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: January 2, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Naoto Abe
  • Patent number: 9768779
    Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Krishnakumar Nadkarni, Stephen Edward Liles, Manish Garg
  • Patent number: 9747850
    Abstract: To realize a level shift circuit with the small occupation area and capable of performing high-speed operation, a level shift circuit includes an electric potential converting unit that converts a first electric potential of an input signal to a third electric potential and converts a second electric potential of an input signal to a fourth electric potential. A capacitor includes first and second electrodes, the first electrode being electrically connected to the input unit, and the second electrode being electrically connected to an output node of the electric potential converting unit. A buffer unit converts the third and fourth electrical potentials to fifth and sixth electrical potentials, respectively. The capacitor reflects the input signal in the electric potential of the output node of the electric potential converting unit without delay by capacitive coupling, thereby realizing a level shift circuit that is capable of performing high-speed operation.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 29, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 9742407
    Abstract: A circuit is disclosed that includes a first switch unit, a first level shift unit and a second level shift unit. The first switch unit is configured to receive a first dynamic input voltage, and to generate a first operation voltage at a first operation terminal or generate a second operation voltage at a second operation terminal according to the first dynamic input voltage. The first level shift unit is coupled to the first switch unit at the first operation terminal, and is configured to shift the first operation voltage to a first output voltage having a first level at an output terminal according to a first supply voltage. The second level shift unit is coupled to the first switch unit at the second operation terminal, and is configured to shift the second operation voltage to the first output voltage having a second level according to a second supply voltage.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 22, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ming-Liang Li
  • Patent number: 9727519
    Abstract: Methods and systems are described for emulating a bi-directional synchronous communications protocol for bi-directional bus communication using unidirectional channels between a master device and a slave device. The master device includes a physical interface to the unidirectional channels that resynchronizes outgoing and incoming data streams in order to reconstruct a bitstream that is compliant with the bi-directional synchronous communications protocol. The reconstructed bitstream is input to the master digital interface controller as though it had been received from the slave device.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 8, 2017
    Assignee: BlackBerry Limited
    Inventor: Jerrold Richard Randell
  • Patent number: 9722610
    Abstract: Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 9685203
    Abstract: A power supply voltage switching circuit includes a power selecting module, a level shifting module, and a supply switching module. The power selecting module receives a first supply signal and a second supply signal, and outputs an intermediate supply signal according to the first supply signal and the second supply signal. The level shifting module receives the intermediate supply signal as a power supply, and generates a first shifted signal and a second shifted signal by shifting voltage levels of a first control signal and a second control signal respectively. The supply switching module receives the first supply signal and a third supply signal, and generates an output signal according to the first shifted signal, the second shifted signal, the first control signal, and the second control signal.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 20, 2017
    Assignee: eMemory Technology Inc.
    Inventor: Kuo-Chun Huang
  • Patent number: 9660651
    Abstract: An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 23, 2017
    Assignee: DENSO CORPORATION
    Inventors: Takuya Honda, Hirofumi Isomura
  • Patent number: 9653451
    Abstract: A semiconductor arrangement (10) with an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor arrangement (10) comprises a first semiconductor chip (20a) with a first integrated circuit (25a) and a second semiconductor chip (20b) with a second integrated circuit (25b). The semiconductor arrangement has an ESD protection circuit (30). The first semiconductor chip (20a) is isolated otherwise form the second semiconductor chip (20b) and the first integrated circuit (25a) is connected to the second integrated circuit (25b) exclusively via the ESD protection circuit (30).
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 16, 2017
    Assignee: TDK-MICRONAS GMBH
    Inventor: Lothar Schmidt
  • Patent number: 9647665
    Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Takanori Matsuzaki, Shuhei Nagatsuka, Takahiko Ishizu, Tatsuya Onuki
  • Patent number: 9633590
    Abstract: A semiconductor structure is provided. A first conductive layer is formed between a substrate and a first insulating layer. A semiconductor layer is disposed over the first insulating layer. A second conductive layer is formed between a semiconductor layer and a second insulating layer and includes a first segment and a second segment. A third conductive layer is disposed over the second insulating layer. The first insulating layer, the semiconductor layer, the first segment and the second segment constitute a first transistor. The third conductive layer, the semiconductor layer, the first segment and the second segment constitute a second transistor. During a first period, the first and third conductive layers receive a first voltage level and a second voltage level respectively. During a second period, the first and third conductive layers receive a third voltage level and a fourth voltage level respectively.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 25, 2017
    Assignee: INNOLUX CORPORATION
    Inventor: Chia-Hao Tsai
  • Patent number: 9614526
    Abstract: Example apparatus for power-domain assignment, having: a first bus-to-switch interface; a second bus-to-switch interface; a first power-domain bus, coupled to the first bus-to-switch interface; a second power-domain bus, coupled to the second bus-to-switch interface. A set of I/O signal level shifters, coupled between the first and second power-domain buses; a switch including, a set of IP block power coupling outputs; a set of IP block I/O signal paths; and a selection signal input. The switch is coupled to the first and second bus-to-switch interfaces. Wherein, in response to receiving a first signal on the selection signal input, the switch is configure to couple the first power-domain bus to the set of IP block power coupling outputs; and wherein, in response to receiving a second signal on the selection signal input, the switch is configure to couple the second power-domain bus to the set of IP block power coupling outputs.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 4, 2017
    Assignee: NXP B.V.
    Inventor: Ajay Kapoor
  • Patent number: 9576983
    Abstract: A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Patent number: 9529953
    Abstract: A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs).
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: December 27, 2016
    Assignee: The United States of America, as Represented by the Secretary of the Navy
    Inventors: Nackieb M. Kamin, Gregory Lum, Henry Au
  • Patent number: 9529753
    Abstract: The present invention discloses an interface sharing apparatus and method, and a mobile communications terminal. The apparatus includes a control unit, a video processing unit, a switch unit, a detection control unit and a multiplexing interface. The detection control unit is configured to detect a first voltage from the multiplexing interface, and to compare the first voltage with a preset voltage value. If the first voltage is greater than zero and less than or equal to the preset voltage value, the detection control unit controls the switch unit, so that the video processing unit is connected to the multiplexing interface by using the switch unit. If the first voltage is equal to zero or greater than the preset voltage value, the detection control unit controls the switch unit, so that the control unit is connected to the multiplexing interface by using the switch unit.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 27, 2016
    Assignee: Huawei Device Co., Ltd.
    Inventors: Chuang Wang, Zhiyong Tang
  • Patent number: 9515651
    Abstract: A galvanically isolated switch system and method comprising a plurality of switches having at least one terminal in series electrical connection, at least one control input electrically connected to at least one of the plurality of switches, wherein the at least one control input is isolated from direct current voltages and at least one passive component connected across the plurality of switches.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: December 6, 2016
    Assignee: TRIUNE IP LLC
    Inventors: Ross E. Teggatz, Wayne T. Chen
  • Patent number: 9503091
    Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Toshiaki Kirihata, Derek H. Leu, Ming Yin
  • Patent number: 9484911
    Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Wilson Jianbo Chen, Chiew-Guan Tan, Reza Jalilizeinali