Abstract: A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract: A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a clock signal and receiving the clock signal as a power source when the input signal has a first phase, where the signal input circuit amplifies a swing width of the input signal based on a swing width of the clock.

Abstract: Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal. A voltage reference level shifter is configured to selectively level shift the voltage reference signal supplied to the amplifier based on a type of device with which the receiver is communicating. A data signal level shifter is configured to selectively level shift the data signal supplied to the amplifier based on the type of device with which the receiver is communicating.

Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a programmable device. The first P-type FET is coupled between a first power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit board's connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted.

Abstract: Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

Abstract: An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit board's connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted.

Abstract: A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).

Abstract: A differential amplifier circuit receives full range differential input signals, and produces a full range output signal, using CMOS transistors designed for one-half such operating voltage. The positive and negative input signals differentially drive first and second CMOS transistors. The source terminals of such first and second CMOS transistors are coupled to a current steering circuit by a pair of lower protection transistors; the gate terminals of such lower protection transistors are driven by level-shifted counterparts of the positive and negative input signals. The drain terminals of the first and second CMOS transistors are coupled to a common node via a pair of upper protection transistors, the gate terminals of which are also driven by the level-shifted counterparts of the input signals.

Abstract: A circuit for shifting at least one input switching signal includes a CMOS bistable circuit having two branches, and a circuit for accelerating the switching of the bistable circuit. The circuit for accelerating the switching allows an output transistor of each branch to be switched to the off state when an input transistor of the branch switches to the on state. The circuit for accelerating switching includes, for at least one given branch, an associated current mirror generating a turn-off current for the output transistor of the branch on the basis of a turn-on current for the input transistor of the branch.

Abstract: In a level shifter including a latch consisting of two p-channel transistors P1 and P2, when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N2 turns ON, thereby dropping a potential level at a node W2. However, since a p-channel transistor P4 is OFF, no short-circuit current flows from a high voltage supply VDD3 into the ground by way of the transistors P2 and N2. On the other hand, since n- and p-channel transistors N1 and P3 are OFF, both terminals of a node W1 are electrically isolated. But the high voltage supply VDD3 pulls the node W1 up to a high voltage level by way of the p-channel transistors P4 and P1 and another p-channel transistor P5 as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N1 and N2 can be reduced, thus shortening the delay.

Abstract: A level converter for the converting of a first digital signal (U1) having a first voltage range into a second digital signal (U2) having a second voltage range comprising an amplifier (T0) having an input for receiving the first digital signal (U1) and an output for supplying the second digital signal (U2), a series arrangement for controlling the slew-rate of the second digital signal (U2) which comprises at least a first capacitor (C1) and a second capacitor (C2) and which is coupled between the output and the input of the amplifier (T0), and voltage controlling means for controlling the voltages (VC1, VC2) across the at least first and second capacitors (C1, C2). The voltage controlling means comprises at least one voltage source (Vls1, Vls2) for supplying a separate bias voltage to each internal node (N1, N2) of the series arrangement. The value of the separate bias voltage or the values of the separate bias voltages is/are dependent on the values of the first (U1) and the second (U2) digital signals.

Abstract: The power consumed by a voltage translator circuit, such as a TTL-to-CMOS buffer, is substantially reduced by changing the supply voltages provided to the input inverter. By reducing the supply voltage provided to the source of the p-channel transistor of the input inverter, the lowest logic-high TTL voltage applied to the gate turns off the p-channel transistor and turns on the n-channel transistor of the input inverter. By increasing the supply voltage provided to the source of the n-channel transistor of the input inverter, the highest logic-low TTL voltage applied to the gate turns off the n-channel transistor and turns on the p-channel transistor.

Abstract: There is disclosed a data input buffer for buffering external input signals into signals suitable for internal signals in a semiconductor memory device. The data input buffer includes switching means controlled by first and second determination signals; and a buffering circuit which is operated as a SSTL buffer or a LVTTL buffer according to the operation of the switching means.

Abstract: Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer.

Abstract: A circuit and a method are disclosed for a Schmitt trigger stage which converts transistor-transistor logic (TTL) into metal oxide semiconductor (MOS) logic signal levels using all MOS devices. The circuit reduces the standby current of the n-channel transistor of the input section of the Schmitt trigger stage by adding a MOS diode to the bottom the input section. When higher than normal supply voltages are used, the standby current of the p-channel transistor of the input section can be reduced by adding a MOS diode to the top of the input section. In addition, a small MOS transistor, connected across the output Schmitt trigger inverter, eliminates leakage currents in that inverter.

Abstract: The buffer circuit of the invention converts TTL level input signals to CMOS level output signals. The buffer circuit has three inverter stages, in which the output signal of one stage is positively fed back, in order to achieve complete modulation. Because of a current limiting circuit, the current consumption of the buffer circuit does not exceed a defined value. Despite a high switching speed, the power consumption of the circuit is low.

Abstract: The present invention provides an apparatus for providing two different modes of operation for an output driver on an integrated circuit. A first mode provides an open drain driver, such as an enhanced GTL+ driver, for high-speed data transmission. A second mode provides a totem pole output driver, such as a TTL or a LVTLL driver, which does not require additional circuitry for external terminations, as is required for open drain drivers. Thus, one embodiment of the present invention can be characterized as an integrated circuit with an output buffer having a first mode that provides a driver for an open drain bus, and a second mode that provides a totem pole output. This output buffer receives a signal to be outputted from the integrated circuit and a mode select signal that selects between the first mode and the second mode.

Abstract: An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal. A switching system is coupled to the differential amplifier, to supply an external power supply voltage to the differential amplifier under SSTL operating conditions and to supply an internal power supply voltage to the differential amplifier under LVTTL operating conditions. An internal power supply voltage generator is responsive to the external power supply voltage, to generate the internal power supply voltage therefrom. The internal power supply voltage generator supplies the internal power supply voltage to the switching system. The switching system preferably includes a first switch that supplies the external power supply voltage to the differential amplifier in response to an SSTL control signal.

Abstract: A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: A TTL-CMOS output stage for an integrated circuit includes a bipolar transistor and a MOS transistor series connected between the power supply and ground, their common point forming the output terminal of the TTL-CMOS output stage. A first switching control input channel includes an inverter whose input forms the input terminal of the stage and whose output is connected to the gate of the MOS transistor via a resistor. A second switching control input channel includes a second inverter controlled by the first inverter and whose output is connected to the base of the bipolar transistor by means of a second resistor. The resistors make it possible to limit the transient current and the mean current supplied by the bipolar transistor.