Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

Abstract: A capacitor-insulated semiconductor relay includes an RC oscillation circuit, a waveform regulation circuit, a booster circuit, a charging/discharging circuit, and an output circuit. The RC oscillation circuit generates first and second signals that are inverse in phase to each other. The waveform regulation circuit increases rise and fall times of the first signal, and rise and fall times of the second signal. Output signals from the waveform regulation circuit are respectively inputted to first and second high dielectric strength capacitors and that are provided in the booster circuit and connected in parallel to each other. The booster circuit receives the output signals from the waveform regulation circuit to generate a predetermined voltage. The output circuit is driven based on the predetermined voltage.

Abstract: A capacitor-insulated semiconductor relay includes an RC oscillation circuit, a waveform regulation circuit, a booster circuit, a charging/discharging circuit, and an output circuit. The RC oscillation circuit generates first and second signals that are inverse in phase to each other. The waveform regulation circuit increases rise and fall times of the first signal, and rise and fall times of the second signal. Output signals from the waveform regulation circuit are respectively inputted to first and second high dielectric strength capacitors and that are provided in the booster circuit and connected in parallel to each other. The booster circuit receives the output signals from the waveform regulation circuit to generate a predetermined voltage. The output circuit is driven based on the predetermined voltage.

Abstract: Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and outputting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.

Abstract: An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, circuitry for producing an oscillatory output signal having a peak voltage of V volts uses MOS transistor circuitry transistors of which are designed for a maximum port-to-port voltage of substantially less than V volts. A first inverter chain is coupled to an input signal to produce a predriver output signal. A second inverter chain of multiple of inverters including a first inverter produces a driver output signal. Circuitry is provided for AC-coupling the predriver output signal to the second inverter chain, it being configured to translate the predriver output signal to a higher voltage range to produce a translated predriver output signal.

Abstract: System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.

Abstract: Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity.

Abstract: An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, circuitry for producing an oscillatory output signal having a peak voltage of V volts uses MOS transistor circuitry transistors of which are designed for a maximum port-to-port voltage of substantially less than V volts. A first inverter chain is coupled to an input signal to produce a predriver output signal. A second inverter chain of multiple of inverters including a first inverter produces a driver output signal. Circuitry is provided for AC-coupling the predriver output signal to the second inverter chain, it being configured to translate the predriver output signal to a higher voltage range to produce a translated predriver output signal.

Abstract: A serial data receiving apparatus includes a transistor, a resistor, and a diode, converts input data of an RS232 standard to data of a TTL/CMOS standard.

Abstract: A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

Abstract: A CMOS based input buffer suitable for use with PECL or LVPECL voltage levels is described. The input buffer utilizes a differential voltage comparator that employs positive feedback to provide input hysteresis, symmetric headroom and increased noise immunity. In addition, the input buffer can utilize a reference voltage that is substantially constant over process, voltage, and temperature.

Abstract: A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.

Abstract: A low frequency detector circuit includes a differential input that is received by an offset comparator circuit. The offset comparator circuit provides respective output signals COMPX and COMPY which can be compared to a generated threshold voltage Vcomp by an E2C (ECL to CMOS) comparators. The outputs of the E2C comparators are used by respective timers to generate fault signals. In addition to detecting low frequency conditions, common voltage conditions can be detected as well and can be distinguished at very high frequency conditions.

Abstract: An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.

Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.

Abstract: The invention relates to a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), and to a network element for transmitting signals which comprises a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), with the level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2).

Abstract: An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The output buffer portion has an input connected to an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). Control power switches driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The CMOS buffer transistors are selectively enabled to control output drive current. Selectable pull-up and pull-down reference circuits provide references (VRFPU, VRFPPU, VRFPD and VRFPPD) to control the current of the buffer output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.

Abstract: An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL.

Abstract: A semiconductor integrated circuit device includes a level-shifting circuit, a current mirror circuit and a switch circuit. The level-shifting circuit level-shifts an input signal having a first amplitude to an output signal having a second amplitude. The current mirror circuit charges or discharges an output node of the level-shifting circuit. The switch circuit operates the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.

Abstract: An CMOS ECL output buffer has a CMOS differential amplifier. A CMOS reference circuit supplies a reference to a reference input of the CMOS differential amplifier. The reference has a high-state value suitable for use by ECL. A CMOS feedback circuit couples a buffer output as negative feedback to a feedback input of the CMOS differential amplifier. A CMOS output circuit supplies an output of the CMOS differential amplifier as the buffer output in response to an input. The buffer output is provided to the ECL. Accordingly, the buffer output is low when the input is low, and the buffer output has the high-state value when the input is high.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A CMOS ECL input buffer buffers signals from an ECL circuit to a CMOS circuit. The CMOS ECL input buffer has a CMOS differential amplifier. A CMOS input circuit is coupled between a buffer input that receives the ECL circuit and a first input of the CMOS differential amplifier. The CMOS input circuit couples an input signal to the first input of the CMOS differential amplifier, and the input signal has an input voltage swing. A reference circuit provides a reference to a second input of the CMOS differential amplifier. The reference is nominally set at substantially a midpoint of the input voltage swing. A CMOS output circuit is coupled between the output of the CMOS differential amplifier and the buffer output, and is arranged to provide an output signal to the buffer output. The output signal, in response to the CMOS differential amplifier, swings between a typical CMOS positive source voltage and ground as the input signal traverses the reference.

Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: A signal level adjusting circuit includes a first amplifying stage in which output electrodes of output stage transistors are connected to ground through current supplies and are connected with respective output terminals, and a DC voltage at the output terminals has a first voltage value; a second amplifying stage in which control electrodes of input stage transistors are connected with respective input terminals, and a DC voltage at the input terminals has a second voltage value; and a coupling stage, connected between the output terminals and the input terminals, which includes at least one series resistor. The first amplifying stage is incorporated in a bipolar IC, and the second amplifying stage is incorporated in a CMOS IC.

Abstract: A CMOS PECL-rx of the present invention comprises a decision stage, an output buffer; and biasing means for adjusting the tip voltage of the output buffer by negative feedback.

Abstract: Such a configuration is provided that a clamp circuit and a level shifting circuit are connected to an output of a source-follower circuit connected to a positive power supply, to apply a negative power supply via a transmission line and a terminating resistor to an output end of the level shifting circuit. With this, a CMOS-level logic signal input to the source-follower circuit is shifted in level toward a level of the negative power supply side. In this case, that signal is clamped by the clamp circuit, during which thus level-shifted signal is shifted in level by the level shifting circuit further toward the negative power supply side, thus permitting an ECL-level signal to pass through the transmission line and appear across the terminating resistor in order to be subsequently applied to an ECL logic circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a differential intermediate signal in response to a differential input signal. The second circuit may be configured to generate one or more output signals in response to said differential intermediate signal.

Abstract: A circuit for converting a negative ECL level to a positive CMOS level is formed by a level conversion circuit input terminal 4 for inputting a negative ECL level, a level shifter 5, one end of which is connected to the input terminal 4, a load 6 of the level shifter 5, one end of which is connected to the level shifter 5 and the other end of which is connected to a positive power supply VDD, and a positive ECL-CMOS level converter 7 for comparing a voltage that is level shifted by the level shifter 5 with a reference voltage Vref and converting to a CMOS level.

Abstract: An input-output circuit in which, even if variations in logic threshold voltages occurs, a logic signal can be exactly recognized on the basis of small-amplitude signals supplied.

Abstract: Disclosed is a synchronous type flip-flop circuit of a semiconductor device including a first clock buffer unit for buffering a complement signal of a data signal input at a first potential level of a clock signal. A second clock buffer unit buffers a complement signal of a signal output from the first clock buffer unit at the first potential level of the clock signal. A precharge latch unit precharges a first node and a second node with a supply voltage at the first potential level of the clock signal, differentially amplifying respective potentials of the first and second nodes by output signals from the first and second clock buffer units at a second potential level of the clock signal, and outputting the amplified signals while latching the amplified signals. The synchronous type flip-flop circuit of the present invention has no requirement to take into consideration problems associated with a transistor ratio. This enables a reduced circuit area and an increased operating speed.

Abstract: An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL.

Abstract: A symmetrical loading and current supply arrangement is described for a differential-type logic means, and symmetrical voltage swings are thereby achieved in the logic output. In a preferred arrangement the output voltages are self-aligned to a CMOS level which facilitate conversion of the differential-type output to CMOS signals.

Abstract: A driver circuit is presented for producing particular output voltage levels at high speeds using a current switching technique. The circuit employs driver transistors connected in series between switchable current sources. The driver transistors switch current within the current sources through a resistor coupled between an output of the driver circuit and a reference terminal voltage. Switching the current occurs in rapid fashion within an opened loop arrangement. The switchable current sources are configured so that current is present through the current sources whenever a corresponding driver transistor is turned on. Current through the current sources, as switched through the resistor separating the reference terminal voltage and the driver output, is regulated by a closed loop replica circuit. The replica circuit may include an opamp whose output operably produces the regulated current via feedback from the current path to an input of the opamp.

Abstract: An emitter-coupled logic to CMOS logic converter includes a first current mirror having a first transistor that has a terminal. The first current mirror is operable to mirror a current in the terminal of the first transistor to produce a mirrored first current. The converter also includes a first current sink operable to generate a first current in the terminal of the first transistor. The converter also includes a second current mirror having a second transistor that has a terminal. The second current mirror is operable to mirror a current in the terminal of the second transistor to produce a mirrored second current. The converter further includes a second current sink operable to generate a second current in the terminal of the second transistor and a differential input pair operable to receive a differential voltage input and direct a current, based on the differential voltage input, to the terminal of the first transistor or the terminal of the second transistor.

Abstract: A CMOS implemented output buffer (10) provides ECL level output signals. The output buffer (10) is implemented in two stages. The first stage (36) includes an inverter having a resistor (39) in series with a P-channel transistor (38) and an N-channel transistor (40) and provides the initial buffering. The resistor (39) in the first inverter stage (36) is used to reduce a cross-over current in the second drive stage (42). The second stage (42) provides additional drive capability and includes an integral level converter. The integral level converter is implemented as a P-channel transistor (44) connected in series with the P-channel and N-channel output driver transistors (53 and 55). The P-channel transistor (44) provides the level shifting function to ECL levels for the second stage. The bias level of the P-channel transistor (44) determines the output logic swing.

Abstract: A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P-channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.

Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

Abstract: A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.

Abstract: A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages.

Abstract: A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

Abstract: An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.

Abstract: Delay time characteristics of rise time and fall times of an output in a CMOS output buffer converting CMOS logic signals into ECL logic signals are made coincident with each other to eliminate various kinds of bias-voltage power supplies required for discharging the charge of capacitance parasitically present on an output-side. The amplifier 1 amplifies an input and supplies a driving input for an outputting P-channel MOSFET 2. A bypass control circuit 4, which inputs gate signals 1001 from the amplifier 1 and a drain potential of the outputting P-channel MOSFET 2 from an output terminal 105, acts as a NAND circuit of those two inputs, and feeds gate signals 1002 so as to cause conduction of the bypassing P-channel MOSFET only at a transient period during which a "high" level outputted to the output terminal 105 is converted into a "low" level, thus the charge on a load capacitance parasitically arisen on the output terminal 105 side is discharged.

Abstract: A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P-channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.

Abstract: A means of converting low voltage CMOS logic levels operating with a 3.3 volts logic level to low voltage PECL logic levels operating with a 3.3 volts supply voltage and a 0.8 volts logic level. The circuit design is process insensitive, and the characteristics of the converter emulate the emitter follower outputs of ECL devices. The converter solves the signal ringing problems caused by open output conditions, and is less susceptible to electromagnetic interference.

Abstract: A level conversion circuit is provided which can obtain a stable output voltage, with keeping low power consumption and a high speed operation, if manufacturing processes and operational conditions of the LSI'S are varied.

Abstract: A buffer circuit for converting logic signals generated by apparatus implemented in a TTL technology to logic signals processed by apparatus implemented by the CMOS technology includes an input stage (10, 11, 12, 13, 17), a voltage-control (14, 15) stage for causing the buffer circuit to vary the input voltage level required to switch the state of the buffer circuit output signal, and a hysteresis stage (16) for causing the switching of the output signal level to be different for the rising and falling edges of the input signal. The voltage-control stage (14, 15) provides a improvement in the noise margin of both the VTTL(High) switching level and the VTTL(Low) switching level.