Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.

Abstract: Various embodiments relate to an EM signal control circuit, an EM signal control method, and an organic light emitting display device. The EM signal control circuit according to an embodiment of the present invention includes additional elements (e.g., a transistor and a capacitor) configured to separate a set signal from a gate electrode of a transistor coupled to an output node and to stably keep turn-off of a transistor coupled to the output node. Voltage levels of a first emission power source and a first gate power source may be set differently from each other according to the present invention. Therefore, despite of a threshold voltage change of a transistor coupled to an output node, the transistor may remain turned off stably, thereby improving the reliability of the EM signal.

Abstract: To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI?NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

Abstract: A signal output circuit is disclosed that supplies a signal from a first circuit that is driven based on a first reference voltage to a second circuit that is driven based on a second reference voltage. The signal output circuit includes a first control circuit that draws a current to the first reference voltage according to an output signal from the first circuit and supplies a signal to the second circuit according to the drawn current, and a second control circuit that draws a current from the second circuit to the second reference voltage.

Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.

Abstract: The invention relates to a circuit of which the operating rate varies according to temperature, supply voltage and intrinsic quality of the transistors of the circuit, associated to a compensating circuit which comprises a constant current source (26) that produces a substantially constant current which is independent of temperature, supply voltage and intrinsic quality of the transistors of the circuit, a variable current source (28) producing a current that increases in an inverse proportion to temperature, supply voltage and intrinsic quality of the transistors of the circuit, and means for decreasing the operating rate of the circuit when the difference of the currents produced by the first and second sources increases.

Abstract: A semiconductor integrated circuit device includes a level-shifting circuit, a current mirror circuit and a switch circuit. The level-shifting circuit level-shifts an input signal having a first amplitude to an output signal having a second amplitude. The current mirror circuit charges or discharges an output node of the level-shifting circuit. The switch circuit operates the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.

Abstract: An CMOS ECL output buffer has a CMOS differential amplifier. A CMOS reference circuit supplies a reference to a reference input of the CMOS differential amplifier. The reference has a high-state value suitable for use by ECL. A CMOS feedback circuit couples a buffer output as negative feedback to a feedback input of the CMOS differential amplifier. A CMOS output circuit supplies an output of the CMOS differential amplifier as the buffer output in response to an input. The buffer output is provided to the ECL. Accordingly, the buffer output is low when the input is low, and the buffer output has the high-state value when the input is high.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: An emitter coupled logic circuit with a data reload function is disclosed. The emitter coupled logic (ECL) circuit includes first and second in series transistors consisting of bipolar junction transistors (BJTs) and field effect transistors (FETs), respectively. The bipolar junction transistor receives a reload signal, and the field effect transistor receives a reload data. Therefore, using the serial control of the bipolar junction transistors together with the field effect transistors, the digital reload data may be reloaded into the ECL circuit. Since the invention utilizes the field effect transistors to directly receive and set the reload data, it is not necessary to pre-convert the digital reload data into a front-stage ECL voltage level. In addition, because the reload data can be sent to the field effect transistors before the reload signal enables, the field effect transistors may be set to ON or OFF in advance.

Abstract: This invention provide a novel class of voltage translators that translate a set of input logic levels (e.g., Low=0 V and High=5 V) to a set of output logic levels (e.g., Low=−4 V and High=0 V), and vice versa, and consume no static power. In contrast to the prior art voltage translators, the output levels provided by the voltage translators of the present invention are stable and predictable, undisturbed by the state of power supply in the systems. The voltage translators of the present invention are simple in design, yet reliable and versatile in performance. They can be easily adapted to a variety of applications.

Abstract: A circuit (10) for providing TTL logic signals at an output (24) employs dual pull up devices (20, 30) at the output. The first device (20) is a bipolar transistor that acts as an emitter-follower to quickly pull up the output in response to applied logic signals to drive the output to a logic one state. Thereafter, the second device (30) which is a MOS transistor is turned on to drive the magnitude of the high logic output signal to substantially VCC, the positive power supply voltage supplied to the circuit (10).

Abstract: A CML-CMOS conversion circuit according to this invention includes: a differential circuit in which resistance is connected as load; a first current mirror circuit made up from an n-channel MOS transistor connected to one output of the differential circuit; a second current mirror circuit made up from an n-channel MOS transistor connected to the other output of the differential circuit; a third current mirror circuit made up of two p-channel MOS transistors connected in series to the first current mirror circuit and the second current mirror circuit; and a CMOS inverter that takes as input the output signal of the second current mirror circuit and that outputs a signal at CMOS logic amplitude.

Abstract: A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

Abstract: A CMOS circuit is disclosed for translating a signal from CML to CMOS logic voltage levels. The CMOS circuit includes two amplifier circuits coupled in parallel. The first amplifier circuit comprises of a programmable circuit and a CMOS inverter such that the CMOS inverter can be programmed "on" or "off" by the programmable circuit. The programmable circuit includes a programmable element which may be implemented using a fuse or floating gate technology. The second amplifying circuit comprises of a CMOS inverter. When the CMOS inverter in the first amplifier circuit is powered "on", the CMOS circuit is operating in a full power mode at high speed with both CMOS inverters operating. When the CMOS inverter in the first amplifier circuit is powered "off", the CMOS circuit is operating in a low power mode at a slower speed with only one CMOS inverter operating.