Security (e.g., Access Or Copy Prevention, Etc.) Patents (Class 326/8)
  • Patent number: 10855690
    Abstract: A secret is stored in a computing device. The device generates a value determined based at least in part on a substantially random process. As a result of the value satisfying a condition, the device causes the secret to be unusable to perform cryptographic operations such that the device is unable to cause the secret to be restored. The secret may be programmatically unexportable from the device.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory Branchek Roth, Gregory Alan Rubin
  • Patent number: 10797891
    Abstract: A physically unclonable function (PUF) system is provided. The PUF system includes an entropy source, a plurality of selectable paths, a random selection block, and error correction logic. The plurality of selectable paths are formed between the entropy source and an output for providing a PUF response. The random selection block is for randomly selecting one of the plurality of selectable paths in response to receiving a challenge. The error correction logic is coupled to the output for receiving the PUF response and for correcting any errors in the PUF response for the plurality of selectable paths. By using a different path through the entropy source each time a challenge is received, protection is provided against side-channel attacks.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 6, 2020
    Assignee: NXP B.V.
    Inventor: Xiaoxu Yao
  • Patent number: 10761809
    Abstract: A random number generator includes an entropy source comprising a first digital device arranged to apply to an input signal a first delay value to obtain a first signal and a second digital device arranged to apply to the input signal a second delay value different from the first delay value to obtain a second signal; a sampling unit configured to sample one of the first and second signals using the other signal as reference clock, thereby obtaining a sampled signal; measurement means to perform measurements of the sampled signal's delay difference with respect to the reference clock; a controller circuit arranged to monitor the measured delay difference of the sampled signal and to check the values of the measured delay difference and, once a given condition related to the values is met, to output a configuration signal.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 1, 2020
    Assignee: KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Adriaan Peetermans, Vladimir Rozic, Ingrid Verbauwhede
  • Patent number: 10712385
    Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output maybe generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 14, 2020
    Assignee: CRYPTOGRAPHY RESEARCH INC.
    Inventors: Michael Hutter, Matthew Pond Baker
  • Patent number: 10649735
    Abstract: A security system with entropy bits includes a physically unclonable function circuit, and a security key generator. The physically unclonable function circuit provides a plurality of entropy bit strings. The security key generator generates a security key by manipulating a manipulation bit string derived from the plurality of entropy bit strings according to an operation entropy bit string. Each bit of the operation entropy bit string is used to determine whether to perform a corresponding operation to the manipulation bit string.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 12, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
  • Patent number: 10615989
    Abstract: One of the various aspects of the invention is related to suggesting various techniques for improving the tamper-resistibility of hardware. The tamper-resistant hardware may be advantageously used in a transaction system that provides the off-line transaction protocol. Amongst these techniques for improving the tamper-resistibility are trusted bootstrapping by means of secure software entity modules, a new use of hardware providing a Physical Unclonable Function, and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Emsycon GmbH
    Inventor: Heinz Kreft
  • Patent number: 10594497
    Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor which are respectively coupled to gate electrodes. An insulation property of a gate insulating film of the first field effect transistor is broken down. A resistance value of the gate insulating film of the second field effect transistor is greater than a resistance value of the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 17, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiromichi Takaoka
  • Patent number: 10572695
    Abstract: A tamper-proof computing device used in conducting a point-of-sale transaction. The tamper-proof computing device comprises a touch-screen display. In some embodiments, an ITO layer is deposited on the touch-screen display that has a tamper line embedded in the ITO layer, such that the tamper line is susceptible to breaking upon unauthorized physical manipulation, and the tamper line is in communication with a microcontroller that is configured to detect the tamper, and to render the tamper-proof computing device inoperable. The tamper line can be a single line trace embedded in the ITO layer or a cluster of traces embedded in the ITO layer. A method of manufacturing comprises forming a tamper line in an ITO layer, depositing the ITO layer on the display and coupling the tamper line to a security microcontroller.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 25, 2020
    Assignee: Square, Inc.
    Inventors: Max Guise, Isreal Blagdan, Bradley T Hall, Trent Weber
  • Patent number: 10511309
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee, Jui-Che Tsai
  • Patent number: 10484188
    Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys. and thereby is immune to traditional database hacking attacks.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 19, 2019
    Assignee: Arizona Board of Regents on behalf of Northern Arizona University
    Inventor: Bertrand Francis Cambou
  • Patent number: 10474796
    Abstract: A method of writing data to a memory device and reading data from the memory device includes issuing a challenge to a PUF device during a power-up process in order to derive a PUF response, error correcting the PUF response, providing delinearized addresses via a delinearization algorithm to the memory device using the error corrected PUF response, masking data, which is written to the memory device, via a masking module using the error corrected PUF response, de-masking data, which is read from the memory device, via the masking module (19) using the error corrected PUF response; and performing a check-sum verification of read data such that address delinearization and data masking are used together to obfuscate the memory content.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 12, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventor: Ciprian-Leonard Pitu
  • Patent number: 10361700
    Abstract: A process variation evaluation method and a process variation evaluating device are provided. The process variation evaluation method is adapted to an electronic device having a PUF device, a recording array and a controller, and includes: iteratively powering up the PUF device in various conditions and detecting a state change of each of the PUF cells in the PUF device by the controller, in which the controller compares a current state in a current iteration and a previous state in a previous iteration of each PUF cell to detect the state change and setting a value indicating the state change in a corresponding bit in the recording array; counting a number of bits with the set value in the recording array after a plurality of iterations; and evaluating a variation of a process according to the counted number by the controller.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10332589
    Abstract: An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Ambiq Micro, Inc.
    Inventors: Scott Hanson, Christophe J. Chevallier
  • Patent number: 10324436
    Abstract: A system of hardware configuration of a programmable control instrument, test and measure that includes an integrated FPGA is disclosed. The FPGA includes a static section comprising at least one static logic FPGA preset; a dynamic section comprising at least one dynamic logic FPGA programmable by a user; and a logical interface that connects the static section and dynamic section.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 18, 2019
    Assignee: Keysight Technologies Singapore (Sales) Pte. Ltd.
    Inventors: Nestor Hugo Oliverio, Marc Almendros Parra
  • Patent number: 10320573
    Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF NORTHERN ARIZONA UNIVERSITY
    Inventor: Bertrand Francis Cambou
  • Patent number: 10289840
    Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 14, 2019
    Assignee: SILICON LABORATORIES INC.
    Inventors: Javier Elenes, Sebastian Ahmed, Lars Lydersen
  • Patent number: 10282552
    Abstract: A method and apparatus is disclosed for protecting electronic devices from security breaches (e.g., in the form of DPA attacks) by managing input/output (I/O) pin states. The technique is particularly useful in financial applications in which data security related operations, such as those involving cryptography, are performed by payment card readers, and the power supplied to drive the operations are measured and analyzed by attackers to extract sensitive information. The technique prevents any external device from measuring the operation power by disabling the I/O pins. The I/O pins are set to a logic low at any given time a data security related operation is performed. As a result, no communication with the external environment is possible during the data security operation, and external power measurements by DPAs are prevented.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 7, 2019
    Assignee: Square, Inc.
    Inventor: Jeremy Wade
  • Patent number: 10243749
    Abstract: A physical unclonable function (PUF) circuit and a PUF system including the same are provided. The PUF circuit includes a plurality of PUF cells each configured to generate an output voltage by dividing a power voltage, a reference voltage generator configured to generate a first reference voltage by dividing the power voltage, and a comparing unit configured to sequentially compare the output voltages of the plurality of PUF cells with the first reference voltage to output data values of the plurality of PUF cells.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-wook Park, Dae-hyeon Kim, Mi-jung Noh, Bohdan Karpinskyy, Yong-ki Lee, Yun-hyeok Choi
  • Patent number: 10235517
    Abstract: An apparatus includes a finite state machine and a physical structure capable of providing a response to a challenge, the physical structure such that before the physical structure is ever provided with the challenge, the response to the challenge is unpredictable. The finite state machine moves from an initial state to an intermediate state due to receiving the response from the physical structure, and moves from the intermediate state to a final state due to receiving a key. The final state indicates whether the physical structure is a counterfeit physical structure.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: March 19, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Yingjie Lao, Keshab K. Parhi, Hyung-il Kim
  • Patent number: 10185820
    Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 22, 2019
    Assignee: Arizona Board of Regents on behalf of Northern Arizona University
    Inventor: Bertrand Francis Cambou
  • Patent number: 10177922
    Abstract: The various technologies presented herein relate to enabling a value generated based upon a physical unclonable function (PUF) response to be available as needed, while also preventing exposure of the PUF to a malicious entity. A masked PUF response can be generated based upon applying a function to a combination of the PUF response and a data file (e.g., a bitstream), and the masked PUF response is forwarded to a requesting entity, rather than the PUF response. Hence, the PUF is masked from any entity requiring access to the PUF. The PUF can be located in a FPGA, wherein the data file is a bitstream pertinent to one or more configurable logic blocks included in the FPGA. A first masked PUF response generated with a first data file can have a different value to a second masked PUF response generated with a second data file.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: January 8, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason Hamlet, Ryan Helinski, Todd Bauer, Lyndon G. Pierson
  • Patent number: 10103733
    Abstract: An integrated circuit (IC) based physically unclonable function (PUF) that comprises a common source amplifier for generating PUF output voltages, a unity gain, negative feedback operational amplifier for generating bias voltages, a voltage regulator and a bit exclusion circuit that excludes unstable PUF bits. Compensation circuitry built into the IC-PUF provides a high power supply rejection ratio and enables highly reliable operation of the IC-PUF across varying input voltages and operating temperatures. The IC-PUF generates a uniformly random output bit stream by taking advantage of process variations that are inherent to the fabrication of (metal-oxide semiconductor) MOS transistors.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 16, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Thomas M. Gurrieri, Jason R. Hamlet, Todd M. Bauer, Ryan Helinski, Lyndon G. Pierson
  • Patent number: 10056905
    Abstract: Techniques are provided for a physically unclonable function (PUF) device. One example PUF device includes, a readout integrated circuit (ROIC) (such as a ROIC for a focal plane array or other imaging application), a nanomaterial-based PUF layer on the ROIC, and a common electrode on the PUF layer. The nanomaterial is randomly distributed throughout the PUF layer. A method of using a PUF device that includes a nanomaterial-based PUF layer coupled to a ROIC, where the nanomaterial is randomly distributed throughout the PUF layer, includes driving the ROIC at a plurality of locations coupled to a corresponding plurality of locations of the PUF layer, sensing the nanomaterial at the locations of the PUF layer, and generating a unique identification key from the sensed locations of the PUF layer. The method can be used, for example, for secure decryption or for identifying or authenticating the PUF device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 21, 2018
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Michael J. Bowers, II, Pierre-Alain S. Auroux, Thomas E. Collins, III, James A. Stobie
  • Patent number: 9990030
    Abstract: An apparatus for the electronic display of information, where the apparatus is a substrate incorporating a digital recording medium attached to or embedded within the substrate. The substrate further includes a flexible-substrate display located on an exposed surface of the substrate, where the display is a medium capable of selectively displaying one of at least two possible colors at each pixel location thereon in order to produce a substrate medium that may be modified in accordance with a user's selection.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: June 5, 2018
    Assignee: Edged Display Management LLC
    Inventor: Michael L. Weiner
  • Patent number: 9985975
    Abstract: A hardware secret is securely maintained in a computing device. The device operates in accordance with a usage limit corresponding to a limited number of operations using the hardware secret that the device is able to perform. Once the device reaches a usage limit, the device becomes temporarily or permanently unable to perform additional operations using the hardware secret.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 29, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory Branchek Roth, Gregory Alan Rubin
  • Patent number: 9967249
    Abstract: A distributed passcode verification system includes devices that each have a secret and that are each able to perform a limited number of verifications using their secrets. Passcode verifiers receive passcode information from a passcode information manager. The passcode information provides information usable, with a secret, to verify passcodes provided to a verifier.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory Branchek Roth, Gregory Alan Rubin
  • Patent number: 9966954
    Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: May 8, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Kaiyuan Yang, David Theodore Blaauw, Dennis Michael Chen Sylvester
  • Patent number: 9930768
    Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machine Corporation
    Inventors: Michael J. Fisher, Roger S. Krabbenhoft
  • Patent number: 9904590
    Abstract: A semiconductor integrated circuit includes a logic circuit including a plurality of storage elements which can each store 1-bit information and an attack detection circuit, the attack detection circuit includes an error determination circuit which can detect through a logic operation that errors have occurred in codes stored in said a plurality of storage elements, and a light irradiation detection circuit which has a light detection element and can detect light irradiation, a light detection element is disposed in the center of area for detecting light irradiation surrounding a plurality of storage elements. It is determined that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Amanuma, Takanori Miyoshi
  • Patent number: 9830445
    Abstract: Biometric information is used to generate a one-time passcode in a two factor authentication process. A current biometric sample is obtained from a user requesting access to a secure resource, together with a user identifier and a current token code. A bio-hash value that encodes a distinct biometric identifier of the authentic user for the user identifier, combined with the authentic user's PIN, is retrieved. A computed PIN is generated based on biometric information extracted from the current biometric sample and the bio-hash value. The computed PIN is combined with the current token code to generate a one-time passcode. The one-time passcode and the user identifier are conveyed to an external user identity verification process that uses the one-time passcode to validate the computed PIN and current token code contained in the one-time passcode.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 28, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: Salah Machani
  • Patent number: 9811507
    Abstract: Information is presented to a user by accessing a library of electronic publications that includes a first publication, generating a representation of the first publication in an electronic bookshelf, determining a state for the first publication and modifying the representation of the first publication to reflect the state of the first publication.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 7, 2017
    Assignee: Apple Inc.
    Inventors: Elizabeth Caroline Furches Cranfill, David Heller, Jeffrey Robbin, Alan C. Cannistraro, William Martin Bachman, Timothy B. Martin, Matt Evans, Joe R. Howard
  • Patent number: 9806719
    Abstract: An apparatus is described. The apparatus includes a physically unclonable (PUF) circuit having a programmable input. The programmable input is to receive a value that caused the PUF circuit to strengthen its stability or strengthen its instability.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Sudhir K. Satpathy, Vikram B. Suresh
  • Patent number: 9763321
    Abstract: A multi-layered electronic system has a support substrate including at least a primary conductive track; a security layer including at least a conductive security track; an electrically-conductive engagement element in electrical communication with the primary conductive tack, and to which the security layer is mounted so that the conductive security track is in permanent electrical communication with the primary conductive track; and a flexible cover layer which overlies the security layer and which is directly or indirectly secured to the support substrate. The electrical connection between the security layer, conductive engagement element and primary conductive track is interrupted when the conductive security track is broken.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 12, 2017
    Assignee: JOHNSON ELECTRIC S.A.
    Inventors: Alan Roger Morey, Martin Wallace Edmonds, Gregory Tobias Knight, Alex James Cowcher, Paul Alfred Hilson, Steven Mark Smith
  • Patent number: 9721031
    Abstract: Devices, systems and methods are disclosed for anchoring bookmarks to individual words for precise positioning within electronic documents. The bookmarks may be anchored based on user input selecting particular words, based on gaze tracking identifying most recently read words, or based on estimated reading speed. The bookmarks may be a link used to navigate within the document, may be used as an anchor for a new layout after content reflow or may be automatically saved when the e-reader turns off the display to provide the user with a most recently read passage. If a bookmark isn't anchored to specific words by the user, the device may anchor the bookmark to the beginning of a sentence or a paragraph including the recently read words determined using gaze tracking or estimated reading speed.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 1, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Stanton Todd Marcum, Michael Patrick Bacus, Timothy Thomas Gray
  • Patent number: 9680477
    Abstract: Systems and methods to obstruct analysis of a microchip may include an electrical component of a microchip and a photodetector positioned within the microchip. The photodetector may be configured to sense electromagnetic radiation. Circuitry in electrical communication with the photodetector may be configured to initiate an action to obstruct analysis of the electrical component in response to a change in a level of the electromagnetic radiation.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9667419
    Abstract: A method for determining a cryptographic key for a MEMS device includes identifying physical properties for the device. A feature vector having a plurality of values is determined. Each of the values correspond to different physical properties. The cryptographic key is determined from the feature vector. The cryptographic key can be determined using a fuzzy extractor. The cryptographic key can be determined using different feature vectors corresponding to different channels in a device or different MEMS structures in the device.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 30, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Jorge Guajardo Merchan, Heiko Stahl, Matthew Lewis, Andreas Mueller, Ralf Schellin
  • Patent number: 9595495
    Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 14, 2017
    Assignee: Altera Corporation
    Inventor: Dinesh Patil
  • Patent number: 9515835
    Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Sudhir K. Satpathy
  • Patent number: 9489508
    Abstract: Apparatus and method for controlling access to protected functionality of a data storage device. In some embodiments, a plurality of identification (ID) values associated with a data storage device are combined to form a combined ID value. The combined ID value is cryptographically processed using a secret symmetric encryption key in combination with a hash function or a key derivation function to generate a unique device credential for the data storage device. The unique device credential is used as an input to a selected cryptographic function to control access to a protected function of the data storage device.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 8, 2016
    Assignee: Seagate Technology LLC
    Inventors: Monty A. Forehand, Manuel A. Offenberg, Christopher J. DeMattio
  • Patent number: 9477458
    Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic time out determination during a microcontroller driven firmware update. In an embodiment, the method includes selecting by a processor of a server a firmware update to be applied by a microcontroller to firmware of the server and computing a timeout value according to a function based upon a date of production of the server. The method also includes transmitting a request to the microcontroller to apply the selected firmware update to the firmware. Finally, the method includes determining a failure state responsive to detecting a lapse in time from the request beyond the timeout value without response by the microcontroller.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 25, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Albert A. Asselin, Michael H. Nolterieke, David Roberts
  • Patent number: 9244862
    Abstract: A communication and security device for a portable computer is disclosed including a housing, a connector provided on the housing for physical connection to the portable computer, a computer interface coupled to the connector for communicating data with the portable computer, a wireless modem coupled to the computer interface for communicating data between the portable computer and a remote device via a wireless network, a regulator operable to regulate power in the communication and storage device, and a processor coupled to control the regulator, the processor coupled to the wireless modem and arranged to process at least one security command received by the wireless modem to control the regulator in response to the received command.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 26, 2016
    Assignee: ExactTrak Limited
    Inventors: Norman Shaw, John Pragnell
  • Patent number: 9237096
    Abstract: The network relay apparatus is provided. The network relay apparatus includes: a main controller; a relay processor; and, a network interface unit configured to include: a plurality of line interfaces to which physical lines are respectively connected and send and receive a packet to and from outside of the network relay apparatus; a data storage configured to store circuit data; a programmable logic device by with a logic circuit having a predetermined function is realized; a configuration circuit configured to direct the programmable logic device to configure the logic circuit using the circuit data; and a state controller provided in a circuit structure other than the programmable logic device to control state of each of the plurality of line interfaces to one of an active state which allows data transmission and reception and a standby state which prohibits data transmission and reception.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: January 12, 2016
    Assignee: ALAXALA NETWORKS CORPORATION
    Inventors: Kazuyuki Tamura, Tsuyoshi Katou
  • Patent number: 9104895
    Abstract: The invention describes a method for accessing a portable storage data carrier (10) having a controller (12) for managing a standardized storage element (14) and having an additional module (16), wherein a data block is transferred to the storage data carrier (10) in a first transmission protocol. The data block comprises routing information and application data, whereby the routing information contains an identifier which can be detected by the controller (12). Furthermore, it is determined whether a data block received on the storage data carrier (10) contains routing information. The data block is relayed to a storage area (18) of the storage element (14), said storage area being hidden to a terminal (50), when the data block comprises routing information and the routing information comprises, besides the identifier contained therein, at least one further, predetermined parameter indicating the access to the hidden storage area (18).
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 11, 2015
    Assignee: GIESECKE & DEVRIENT GMBH
    Inventor: Ullrich Martini
  • Patent number: 9100361
    Abstract: A routing module in a secure routing and communication architecture to receive and transmit data of varied protocols, convert the data protocols to an internet protocol for routing on a local area network. Components of the input/output module comprise a processor, a cryptomodule, a field programmable gate array, all of which communicate in internet protocol. The routing module has a number of interfaces through which SATCOM protocol, UHF-VHF protocol, digital data protocols, serial data protocols, common data link protocols, push-to-talk data protocols, analog voice and voice internet protocol, and other internet protocol data can be received, routed, and transmitted. Hardware, firmware, and software logic within the components convert analog or other digital data to internet protocol, verify the classification level of data, protect the classification level of the data, encrypt the data for routing through a secure routing system a destination interface.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: August 4, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: Frank A. Lucchesi, Christopher T. Wolff
  • Patent number: 9083323
    Abstract: One feature pertains to an integrated circuit (IC) that includes a first plurality of ring oscillators configured to implement, in part, a physically unclonable function (PUF). The IC further includes a second plurality of ring oscillators configured to implement, in part, an age sensor circuit, and also a ring oscillator selection circuit that is coupled to the first plurality of ring oscillators and the second plurality of ring oscillators. The ring oscillator selection circuit is adapted to select at least two ring oscillator outputs from at least one of the first plurality of ring oscillators and/or the second plurality of ring oscillators. Notably, the ring oscillator selection circuit is commonly shared by the PUF and the age sensor circuit. Also, the IC may further include an output function circuit adapted to receive and compare the two ring oscillator outputs and generate an output signal.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xu Guo, Brian M. Rosenberg
  • Patent number: 9069706
    Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: June 30, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Parthasarathy Sriram, Gordon Grigor, Shu-Jen Fang
  • Patent number: 9048834
    Abstract: A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+1)/2 is an odd number.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Jiangtao Li, Patrick Koeberl, Sanu K. Mathew, Wei Wu
  • Publication number: 20150130506
    Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 14, 2015
    Inventors: Swarup Bhunia, Abhishek Basak, Zheng Yu
  • Publication number: 20150130505
    Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 14, 2015
    Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS
  • Patent number: 9030226
    Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 12, 2015
    Assignee: STC.UNM
    Inventors: James Plusquellic, Dhruva J. Acharyya, Ryan L. Helinski