Security (e.g., Access Or Copy Prevention, Etc.) Patents (Class 326/8)
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Patent number: 8912816Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: February 19, 2014Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 8912815Abstract: A semiconductor integrated circuit includes a logic circuit, the logic circuit including an attack detection circuit for checking multi-bit storage. The attack detection circuit includes an error determination circuit capable of detection through a logic operation such as a code theory and a light irradiation detection circuit having light detection elements, and the light detection elements are arranged so that the light irradiation detection circuit can detect errors of the number of bits beyond the detection limit of the error determination circuit. Due to error detection by the error determination circuit and light irradiation detection by the light irradiation detection circuit, the circuits complementarily detect fault attacks from outside.Type: GrantFiled: September 5, 2013Date of Patent: December 16, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Amanuma, Takanori Miyoshi
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Patent number: 8912817Abstract: A reconfigurable multi-port physical unclonable functions (RM-PUFs) circuit, including: an input signal interface, a first control circuit module, at least two RM-PUFs circuit units, and an output signal interface. Each RM-PUFs circuit unit includes a second control circuit module, an input module, an output module, and a deviation generation module. The input signal interface is connected to the first control circuit module, the first control circuit module is connected to the RM-PUFs circuit units, and the RM-PUFs circuit units are connected to the output signal interface.Type: GrantFiled: March 18, 2014Date of Patent: December 16, 2014Assignee: Ningbo UniversityInventors: Pengjun Wang, Yuejun Zhang, Zhidi Jiang, Jianrui Li
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Patent number: 8912814Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: May 31, 2013Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Publication number: 20140354327Abstract: An apparatus for generating random bits includes a plurality of mapping devices. A respective mapping device is configured to map a predefined number of input signals, with the aid of a combinatorial mapping, into a predefined number of output signals. The plurality of mapping devices are concatenated with one another, and at least one combinatorial mapping is configured such that a state change of an input signal of a respective mapping device is mapped on average onto more than one output signal of the respective mapping device. No feedback loop is present such that a state change of at least one feedback output signal of a specific mapping device is fed as a state change of at least one input signal to another mapping device such that one or a plurality of output signals of the specific mapping device is influenced by the state change of the feedback output signal.Type: ApplicationFiled: May 2, 2014Publication date: December 4, 2014Inventors: Pascale Böffgen, Markus Dichtl
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Patent number: 8904192Abstract: A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.Type: GrantFiled: March 18, 2009Date of Patent: December 2, 2014Assignees: Institut Telecom-Telecom Paris Tech, Centre National de la Recherche Scientifique (CNRS)Inventors: Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst
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Patent number: 8901953Abstract: Technologies for enforcing an expiration policy on an electronic engineering sample component includes a one-time programmable fuse to store a manufacture date of the electronic engineering sample component, another one-time programmable fuse to store an expiration date of the electronic engineering sample component, and a component life management engine to compare a current date of the electronic engineering sample component with the expiration date of the electronic engineering sample component. The component life management engine to disable or lock the electronic engineering sample component in response to determining that the current date of the electronic engineering sample component exceeds the expiration date of the electronic engineering sample component. In some embodiments, a computing device may enforce the expiration policy for the electronic engineering sample component.Type: GrantFiled: September 28, 2012Date of Patent: December 2, 2014Assignee: Intel CorporationInventors: Abdi Nassib, Gyan Prakash
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Patent number: 8901954Abstract: Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.Type: GrantFiled: November 16, 2012Date of Patent: December 2, 2014Assignee: TUBITAKInventor: Umut Guvenc
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Publication number: 20140340112Abstract: Provided are methods, systems, and devices for preventing hardware piracy.Type: ApplicationFiled: March 17, 2014Publication date: November 20, 2014Inventors: Mohammad Tehranipoor, Nicholas Tuzzio
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Patent number: 8885819Abstract: Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: Intel CorporationInventors: Kevin C. Gotze, Jiangtao Li, Gregory M. Iovino
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Publication number: 20140327469Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.Type: ApplicationFiled: September 17, 2013Publication date: November 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dirk PFEIFFER, Jean-Olivier PLOUCHART, Peilin SONG
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Publication number: 20140327468Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.Type: ApplicationFiled: May 3, 2013Publication date: November 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Patent number: 8868923Abstract: Detection and deterrence of spoofing of user authentication may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a user of the hardware device. The cryptographic fingerprint unit includes an internal physically unclonable function (“PUF”) circuit disposed in or on the hardware device, which generates a PUF value. Combining logic is coupled to receive the PUF value, combines the PUF value with one or more other authentication factors to generate a multi-factor authentication value. A key generator is coupled to generate a private key and a public key based on the multi-factor authentication value while a decryptor is coupled to receive an authentication challenge posed to the hardware device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.Type: GrantFiled: October 20, 2010Date of Patent: October 21, 2014Assignee: Sandia CorporationInventors: Jason R. Hamlet, Lyndon G. Pierson
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Publication number: 20140266296Abstract: A reconfigurable multi-port physical unclonable functions (RM-PUFs) circuit, including: an input signal interface, a first control circuit module, at least two RM-PUFs circuit units, and an output signal interface. Each RM-PUFs circuit unit includes a second control circuit module, an input module, an output module, and a deviation generation module. The input signal interface is connected to the first control circuit module, the first control circuit module is connected to the RM-PUFs circuit units, and the RM-PUFs circuit units are connected to the output signal interface.Type: ApplicationFiled: March 18, 2014Publication date: September 18, 2014Applicant: Ningbo UniversityInventors: Pengjun WANG, Yuejun ZHANG, Zhidi JIANG, Jianrui LI
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Patent number: 8816717Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.Type: GrantFiled: October 17, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Gregory M. Fritz, Chung H. Lam, Dirk Pfeiffer, Kenneth P. Rodbell, Robert L. Wisnieff
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Publication number: 20140225639Abstract: One feature pertains to an integrated circuit (IC) that includes a first plurality of ring oscillators configured to implement, in part, a physically unclonable function (PUF). The IC further includes a second plurality of ring oscillators configured to implement, in part, an age sensor circuit, and also a ring oscillator selection circuit that is coupled to the first plurality of ring oscillators and the second plurality of ring oscillators. The ring oscillator selection circuit is adapted to select at least two ring oscillator outputs from at least one of the first plurality of ring oscillators and/or the second plurality of ring oscillators. Notably, the ring oscillator selection circuit is commonly shared by the PUF and the age sensor circuit. Also, the IC may further include an output function circuit adapted to receive and compare the two ring oscillator outputs and generate an output signal.Type: ApplicationFiled: February 11, 2013Publication date: August 14, 2014Applicant: QUALCOMM IncorporatedInventors: Xu GUO, Brian M. Rosenberg
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Patent number: 8803548Abstract: A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.Type: GrantFiled: April 19, 2012Date of Patent: August 12, 2014Assignee: Microsemi SoC CorporationInventor: Robert M. Salter, III
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Publication number: 20140218067Abstract: A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+1)/2 is an odd number.Type: ApplicationFiled: January 16, 2013Publication date: August 7, 2014Applicant: Intel CorporationInventors: Jiangtao Li, Patrick Koeberl, Sanu K. Mathew, Wei Wu
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Patent number: 8797059Abstract: A method and circuit for implementing security protection with carbon nanotube based sensors for cryptographic applications, and a design structure on which the subject circuit resides are provided. A carbon nanotube layer is incorporated with a polymeric encapsulation layer of a security card. Electrical connections to the carbon nanotube layer are provided for electrical monitoring of electrical resistance of the carbon nanotube layer.Type: GrantFiled: March 1, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Dylan J. Boday, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
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Publication number: 20140191781Abstract: Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.Type: ApplicationFiled: November 16, 2012Publication date: July 10, 2014Applicant: TUBITAKInventor: Umut Guvenc
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Publication number: 20140184266Abstract: In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: Yuri I. Krimon, David I. Poisner, Reinhard R. Steffens
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Publication number: 20140176182Abstract: Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data informationType: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Kelin J Kuhn, Christopher J Jezewski, Marko Radosavljevic
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Patent number: 8749265Abstract: Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to an first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node.Type: GrantFiled: December 2, 2009Date of Patent: June 10, 2014Assignee: ICT Korea Co., Ltd.Inventors: Dong Kyue Kim, Byong-Doek Choi
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Patent number: 8745107Abstract: A method for protecting an integrated circuit. According to the method, the start-up of all, or part, of the circuit is determined in the presence of a key which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter which is present in a non-volatile manner in the circuit after the production thereof.Type: GrantFiled: September 27, 2005Date of Patent: June 3, 2014Assignee: STMicroelectronics S.A.Inventors: Luc Wuidart, Fabrice Marinet
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Publication number: 20140145752Abstract: An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.Type: ApplicationFiled: February 25, 2013Publication date: May 29, 2014Applicant: NATIONAL CHENG KUNG UNIVERSITYInventor: CHUNG-HUNG LIN
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Patent number: 8736299Abstract: Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry may also use the security requirement data to set security features within the device.Type: GrantFiled: April 29, 2011Date of Patent: May 27, 2014Assignee: Altera CorporationInventor: Bruce B. Pedersen
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Patent number: 8729922Abstract: Methods and apparatuses for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design through the use of hardware technologies. According to one embodiment, a hardware sub-design includes a license verification sub-design that is protected from user modification by encryption. In one embodiment, a license is generated based on a trusted host identifier within an external hardware device. In one embodiment, each trusted host identifier is unique, and no two integrated circuits share the same trusted host identifier. In another embodiment, the integrated circuit is a field programmable gate array or an application specific integrated circuit. In one embodiment, a license determines how long the hardware sub-design will operate when the hardware sub-design is implemented within an integrated circuit having a trusted host identifier.Type: GrantFiled: July 11, 2011Date of Patent: May 20, 2014Assignee: Synopsys, Inc.Inventor: Kenneth S. McElvain
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Patent number: 8713327Abstract: A circuit for enabling communication of cryptographic data in an integrated circuit is disclosed. The circuit comprises a first interface coupled to receive data having a first security level; a second interface coupled to receive data having a second security level; a cryptographic application; and a routing block coupled between the first and second interfaces and the cryptographic application, the routing block comprising configurable logic, wherein the routing block is configurable to selectively route the data having the first security level by way of the first interface and to route data having the second security level by way of the second interface. A method of enabling communication of cryptographic data in an integrated circuit is also disclosed.Type: GrantFiled: February 2, 2009Date of Patent: April 29, 2014Assignee: Xilinx, Inc.Inventors: Edward S. Peterson, Jason J. Moore
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Publication number: 20140111245Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.Type: ApplicationFiled: May 2, 2013Publication date: April 24, 2014Applicant: eMemory Technology Inc.Inventors: Tung-Cheng Kuo, Sheng-Kai Chen
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Publication number: 20140103957Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: International Business Machines CorporationInventors: Gregory M. Fritz, Chung H. Lam, Dirk Pfeiffer, Kenneth P. Rodbell, Robert L. Wisnieff
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Publication number: 20140091831Abstract: Technologies for enforcing an expiration policy on an electronic engineering sample component includes a one-time programmable fuse to store a manufacture date of the electronic engineering sample component, another one-time programmable fuse to store an expiration date of the electronic engineering sample component, and a component life management engine to compare a current date of the electronic engineering sample component with the expiration date of the electronic engineering sample component. The component life management engine to disable or lock the electronic engineering sample component in response to determining that the current date of the electronic engineering sample component exceeds the expiration date of the electronic engineering sample component. In some embodiments, a computing device may enforce the expiration policy for the electronic engineering sample component.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Abdi Nassib, Gyan Prakash
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Publication number: 20140091832Abstract: An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Kevin C. Gotze, Gregory M. Iovino, Jiangtao Li, David Johnston, Sanu K. Mathew, George W. Cox, Anand Rajan
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Publication number: 20140090093Abstract: A mesh grid protection system is provided. The system includes grid lines forming a mesh grid proximate to operational logic and assertion logic configured to transmit a first set of signals on a first set of grid lines. The system also includes transformation logic coupled to the grid lines and configured to receive the first set of signals and transform the first set of signals to generate a second set of signals and transmit the second set of signals on a second set of grid lines. The system further includes verification logic coupled to the transformation logic and configured to compare the second set of signals to an expected set of signals.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Applicant: Broadcom CorporationInventors: Kambiz RAHIMI, Mark Buer, Rolando Ogot
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Publication number: 20140077835Abstract: A semiconductor integrated circuit includes a logic circuit, the logic circuit including an attack detection circuit for checking multi-bit storage. The attack detection circuit includes an error determination circuit capable of detection through a logic operation such as a code theory and a light irradiation detection circuit having light detection elements, and the light detection elements are arranged so that the light irradiation detection circuit can detect errors of the number of bits beyond the detection limit of the error determination circuit. Due to error detection by the error determination circuit and light irradiation detection by the light irradiation detection circuit, the circuits complementarily detect fault attacks from outside.Type: ApplicationFiled: September 5, 2013Publication date: March 20, 2014Applicant: Renesas Electronics CorporationInventors: Yoshiyuki Amanuma, Takanori Miyoshi
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Publication number: 20140035613Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Marco BUCCI, Raimondo LUZZI
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Patent number: 8610454Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.Type: GrantFiled: January 12, 2011Date of Patent: December 17, 2013Assignee: STC.UNMInventors: James Plusquellic, Dhruva J. Acharyya, Ryan L. Helinski
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Patent number: 8604824Abstract: A hacking detecting device includes a metal line capacitor, a charge providing unit, a charge storing unit and a hacking deciding unit. The metal line capacitor has a first metal line and a second metal line. The charge providing unit periodically charges the metal line capacitor. The charge storing unit accumulates charges periodically stored in the metal line capacitor, and generates an output voltage corresponding to an amount of the accumulated charges. The hacking deciding unit determines whether the metal line capacitor is exposed based on the output voltage of the charge storing unit.Type: GrantFiled: September 22, 2011Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., LtdInventor: Seung-won Lee
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Patent number: 8604823Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.Type: GrantFiled: December 11, 2008Date of Patent: December 10, 2013Assignee: Altera CorporationInventor: Laura Reese
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Patent number: 8605401Abstract: Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.Type: GrantFiled: April 29, 2011Date of Patent: December 10, 2013Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese
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Publication number: 20130314121Abstract: A method for detecting an attack, such as by laser, on an electronic microcircuit from a backside of a substrate includes forming the microcircuit on the semiconductor substrate, the microcircuit comprising a circuit to be protected against attacks, forming photodiodes between components of the circuit to be protected, forming a circuit for comparing a signal supplied by each photodiode with a threshold value, and forming a circuit for activating a detection signal when a signal at output of one of the photodiodes crosses the threshold value.Type: ApplicationFiled: May 23, 2013Publication date: November 28, 2013Inventors: Stephane Mougin, Cedric Tubert
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Patent number: 8593172Abstract: An integrated circuit having secure configuration includes configuration memory, programmable logic resources coupled to the configuration memory, programmable interconnection resources coupled to the configuration memory and programmable logic resources, and a configuration controller circuit coupled to the configuration memory. The configuration controller circuit is configured to read values from a configuration memory address of a portion of the configuration memory in response to a configuration memory address contained in input configuration data, and to decrypt the input configuration data using the values as a decryption key. The configuration controller is further configured to program the configuration memory of the integrated circuit with the decrypted input configuration data.Type: GrantFiled: August 16, 2011Date of Patent: November 26, 2013Assignee: Xilinx, Inc.Inventor: Jesse H. Jenkins, IV
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Publication number: 20130307578Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.Type: ApplicationFiled: April 19, 2013Publication date: November 21, 2013Applicant: NXP B.V.Inventors: Soenke Ostertun, Michael Ziesmann
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Publication number: 20130300453Abstract: A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Applicant: Gilbarco Inc.Inventors: Giovanni Carapelli, Philip A. Robertson, Alberto Tosi
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Patent number: 8581617Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.Type: GrantFiled: April 29, 2011Date of Patent: November 12, 2013Assignee: Altera CorporationInventors: Dirk A. Reese, Bruce B. Pedersen
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Patent number: 8581618Abstract: A system provides for the distribution of intellectual property logic blocks from a source to a user wherein the user may use the logic blocks during development but is prevented from using the block in production without permission. A sensor is connected in parallel with a first signal from the block and in series with a second signal from the block. When activity on the first signal exceeds a predetermined count, the output of the second signal is corrupted. In some embodiments all such sensors are connected to an aggregator which allows all blocks to continue to operate until all of them have exceeded their predetermined activity count. A state machine compares the values of two keys, one stored within the block, to another value stored in the state machine controller, and allows the block to be used in production if the key values coincide.Type: GrantFiled: February 14, 2012Date of Patent: November 12, 2013Assignee: Social Silicon, Inc.Inventor: David Fritz
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Publication number: 20130293259Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.Type: ApplicationFiled: March 11, 2013Publication date: November 7, 2013Inventors: Kazuyuki Tanimura, Nikil Dutt
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Publication number: 20130278284Abstract: To enhance the security of a semiconductor device, the semiconductor device has a regulator unit for generating an internal power supply voltage based on a power supply voltage supplied from outside, an internal circuit which operates on the internal power supply voltage, a current detection unit for monitoring a power supply current supplied to the internal circuit, and a control unit for controlling operation of the internal circuit. In the semiconductor device, when the current detection unit detects that the power supply current exceeds a predetermined threshold value, the control unit restricts the operation of the internal circuit.Type: ApplicationFiled: April 8, 2013Publication date: October 24, 2013Applicant: Renesas Electronics CorporationInventors: Kazuki Watanabe, Yosuke Tanno
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Publication number: 20130271178Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may he implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventors: Bruce B. Pedersen, Dirk A. Reese, Juju Joyce
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Publication number: 20130257473Abstract: A long-life embedded structure sensor, remote long-life fluid measurement and analysis system, long-life off-grid enclosed space proximity change detector, surface-mount encryption device with volatile long-life key storage and volume intrusion response, and a portable encrypted data storage with volatile long-life key storage and volume intrusion response are provided to be powered by and equipped with a long-life power source that can provide operative power for at least a twenty year duration.Type: ApplicationFiled: July 16, 2009Publication date: October 3, 2013Applicant: Lockheed Martin CorporationInventors: Christian Adams, Joseph M. Wright, Patrick A. Nelson, Kenneth S. Gurley, Richard A. Vaughn
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Patent number: 8548071Abstract: An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.Type: GrantFiled: July 19, 2011Date of Patent: October 1, 2013Assignee: Xilinx, Inc.Inventor: Anthony J. Collins