Abstract: An apparatus includes a finite state machine and a physical structure capable of providing a response to a challenge, the physical structure such that before the physical structure is ever provided with the challenge, the response to the challenge is unpredictable. The finite state machine moves from an initial state to an intermediate state due to receiving the response from the physical structure, and moves from the intermediate state to a final state due to receiving a key. The final state indicates whether the physical structure is a counterfeit physical structure.

Abstract: The present invention provides a method for authenticating distributed peripherals on a computer network using an array of physically unclonable functions (PUF). As each PUF is unique, each PUF is able to generate a plurality of challenge response pairs that are unique to that PUF. The integrated circuits of the PUF comprise a plurality of cells, where a parameter (such as a voltage) of each cell may be measured (possibly averaged over many readings). The plurality of cells in the PUF may be arranged in a one, two or more dimensional matrix. A protocol based on an addressable PUF generator (APG) allows the protection of a network having distributed peripherals such as Internet of things (IoT), smart phones, lap top and desk top computers, or ID cards. This protection does not require the storage of a database of passwords, or secret keys, and thereby is immune to traditional database hacking attacks.

Abstract: The various technologies presented herein relate to enabling a value generated based upon a physical unclonable function (PUF) response to be available as needed, while also preventing exposure of the PUF to a malicious entity. A masked PUF response can be generated based upon applying a function to a combination of the PUF response and a data file (e.g., a bitstream), and the masked PUF response is forwarded to a requesting entity, rather than the PUF response. Hence, the PUF is masked from any entity requiring access to the PUF. The PUF can be located in a FPGA, wherein the data file is a bitstream pertinent to one or more configurable logic blocks included in the FPGA. A first masked PUF response generated with a first data file can have a different value to a second masked PUF response generated with a second data file.

Abstract: An integrated circuit (IC) based physically unclonable function (PUF) that comprises a common source amplifier for generating PUF output voltages, a unity gain, negative feedback operational amplifier for generating bias voltages, a voltage regulator and a bit exclusion circuit that excludes unstable PUF bits. Compensation circuitry built into the IC-PUF provides a high power supply rejection ratio and enables highly reliable operation of the IC-PUF across varying input voltages and operating temperatures. The IC-PUF generates a uniformly random output bit stream by taking advantage of process variations that are inherent to the fabrication of (metal-oxide semiconductor) MOS transistors.

Abstract: Techniques are provided for a physically unclonable function (PUF) device. One example PUF device includes, a readout integrated circuit (ROIC) (such as a ROIC for a focal plane array or other imaging application), a nanomaterial-based PUF layer on the ROIC, and a common electrode on the PUF layer. The nanomaterial is randomly distributed throughout the PUF layer. A method of using a PUF device that includes a nanomaterial-based PUF layer coupled to a ROIC, where the nanomaterial is randomly distributed throughout the PUF layer, includes driving the ROIC at a plurality of locations coupled to a corresponding plurality of locations of the PUF layer, sensing the nanomaterial at the locations of the PUF layer, and generating a unique identification key from the sensed locations of the PUF layer. The method can be used, for example, for secure decryption or for identifying or authenticating the PUF device.

Abstract: An apparatus for the electronic display of information, where the apparatus is a substrate incorporating a digital recording medium attached to or embedded within the substrate. The substrate further includes a flexible-substrate display located on an exposed surface of the substrate, where the display is a medium capable of selectively displaying one of at least two possible colors at each pixel location thereon in order to produce a substrate medium that may be modified in accordance with a user's selection.

Abstract: A hardware secret is securely maintained in a computing device. The device operates in accordance with a usage limit corresponding to a limited number of operations using the hardware secret that the device is able to perform. Once the device reaches a usage limit, the device becomes temporarily or permanently unable to perform additional operations using the hardware secret.

Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.

Abstract: A distributed passcode verification system includes devices that each have a secret and that are each able to perform a limited number of verifications using their secrets. Passcode verifiers receive passcode information from a passcode information manager. The passcode information provides information usable, with a secret, to verify passcodes provided to a verifier.

Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.

Abstract: A semiconductor integrated circuit includes a logic circuit including a plurality of storage elements which can each store 1-bit information and an attack detection circuit, the attack detection circuit includes an error determination circuit which can detect through a logic operation that errors have occurred in codes stored in said a plurality of storage elements, and a light irradiation detection circuit which has a light detection element and can detect light irradiation, a light detection element is disposed in the center of area for detecting light irradiation surrounding a plurality of storage elements. It is determined that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation.

Abstract: Biometric information is used to generate a one-time passcode in a two factor authentication process. A current biometric sample is obtained from a user requesting access to a secure resource, together with a user identifier and a current token code. A bio-hash value that encodes a distinct biometric identifier of the authentic user for the user identifier, combined with the authentic user's PIN, is retrieved. A computed PIN is generated based on biometric information extracted from the current biometric sample and the bio-hash value. The computed PIN is combined with the current token code to generate a one-time passcode. The one-time passcode and the user identifier are conveyed to an external user identity verification process that uses the one-time passcode to validate the computed PIN and current token code contained in the one-time passcode.

Abstract: Information is presented to a user by accessing a library of electronic publications that includes a first publication, generating a representation of the first publication in an electronic bookshelf, determining a state for the first publication and modifying the representation of the first publication to reflect the state of the first publication.

Abstract: An apparatus is described. The apparatus includes a physically unclonable (PUF) circuit having a programmable input. The programmable input is to receive a value that caused the PUF circuit to strengthen its stability or strengthen its instability.

Abstract: A multi-layered electronic system has a support substrate including at least a primary conductive track; a security layer including at least a conductive security track; an electrically-conductive engagement element in electrical communication with the primary conductive tack, and to which the security layer is mounted so that the conductive security track is in permanent electrical communication with the primary conductive track; and a flexible cover layer which overlies the security layer and which is directly or indirectly secured to the support substrate. The electrical connection between the security layer, conductive engagement element and primary conductive track is interrupted when the conductive security track is broken.

Abstract: Devices, systems and methods are disclosed for anchoring bookmarks to individual words for precise positioning within electronic documents. The bookmarks may be anchored based on user input selecting particular words, based on gaze tracking identifying most recently read words, or based on estimated reading speed. The bookmarks may be a link used to navigate within the document, may be used as an anchor for a new layout after content reflow or may be automatically saved when the e-reader turns off the display to provide the user with a most recently read passage. If a bookmark isn't anchored to specific words by the user, the device may anchor the bookmark to the beginning of a sentence or a paragraph including the recently read words determined using gaze tracking or estimated reading speed.

Abstract: Systems and methods to obstruct analysis of a microchip may include an electrical component of a microchip and a photodetector positioned within the microchip. The photodetector may be configured to sense electromagnetic radiation. Circuitry in electrical communication with the photodetector may be configured to initiate an action to obstruct analysis of the electrical component in response to a change in a level of the electromagnetic radiation.

Abstract: A method for determining a cryptographic key for a MEMS device includes identifying physical properties for the device. A feature vector having a plurality of values is determined. Each of the values correspond to different physical properties. The cryptographic key is determined from the feature vector. The cryptographic key can be determined using a fuzzy extractor. The cryptographic key can be determined using different feature vectors corresponding to different channels in a device or different MEMS structures in the device.

Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.

Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.

Abstract: Apparatus and method for controlling access to protected functionality of a data storage device. In some embodiments, a plurality of identification (ID) values associated with a data storage device are combined to form a combined ID value. The combined ID value is cryptographically processed using a secret symmetric encryption key in combination with a hash function or a key derivation function to generate a unique device credential for the data storage device. The unique device credential is used as an input to a selected cryptographic function to control access to a protected function of the data storage device.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic time out determination during a microcontroller driven firmware update. In an embodiment, the method includes selecting by a processor of a server a firmware update to be applied by a microcontroller to firmware of the server and computing a timeout value according to a function based upon a date of production of the server. The method also includes transmitting a request to the microcontroller to apply the selected firmware update to the firmware. Finally, the method includes determining a failure state responsive to detecting a lapse in time from the request beyond the timeout value without response by the microcontroller.

Abstract: A communication and security device for a portable computer is disclosed including a housing, a connector provided on the housing for physical connection to the portable computer, a computer interface coupled to the connector for communicating data with the portable computer, a wireless modem coupled to the computer interface for communicating data between the portable computer and a remote device via a wireless network, a regulator operable to regulate power in the communication and storage device, and a processor coupled to control the regulator, the processor coupled to the wireless modem and arranged to process at least one security command received by the wireless modem to control the regulator in response to the received command.

Abstract: The network relay apparatus is provided. The network relay apparatus includes: a main controller; a relay processor; and, a network interface unit configured to include: a plurality of line interfaces to which physical lines are respectively connected and send and receive a packet to and from outside of the network relay apparatus; a data storage configured to store circuit data; a programmable logic device by with a logic circuit having a predetermined function is realized; a configuration circuit configured to direct the programmable logic device to configure the logic circuit using the circuit data; and a state controller provided in a circuit structure other than the programmable logic device to control state of each of the plurality of line interfaces to one of an active state which allows data transmission and reception and a standby state which prohibits data transmission and reception.

Abstract: The invention describes a method for accessing a portable storage data carrier (10) having a controller (12) for managing a standardized storage element (14) and having an additional module (16), wherein a data block is transferred to the storage data carrier (10) in a first transmission protocol. The data block comprises routing information and application data, whereby the routing information contains an identifier which can be detected by the controller (12). Furthermore, it is determined whether a data block received on the storage data carrier (10) contains routing information. The data block is relayed to a storage area (18) of the storage element (14), said storage area being hidden to a terminal (50), when the data block comprises routing information and the routing information comprises, besides the identifier contained therein, at least one further, predetermined parameter indicating the access to the hidden storage area (18).

Abstract: A routing module in a secure routing and communication architecture to receive and transmit data of varied protocols, convert the data protocols to an internet protocol for routing on a local area network. Components of the input/output module comprise a processor, a cryptomodule, a field programmable gate array, all of which communicate in internet protocol. The routing module has a number of interfaces through which SATCOM protocol, UHF-VHF protocol, digital data protocols, serial data protocols, common data link protocols, push-to-talk data protocols, analog voice and voice internet protocol, and other internet protocol data can be received, routed, and transmitted. Hardware, firmware, and software logic within the components convert analog or other digital data to internet protocol, verify the classification level of data, protect the classification level of the data, encrypt the data for routing through a secure routing system a destination interface.

Abstract: One feature pertains to an integrated circuit (IC) that includes a first plurality of ring oscillators configured to implement, in part, a physically unclonable function (PUF). The IC further includes a second plurality of ring oscillators configured to implement, in part, an age sensor circuit, and also a ring oscillator selection circuit that is coupled to the first plurality of ring oscillators and the second plurality of ring oscillators. The ring oscillator selection circuit is adapted to select at least two ring oscillator outputs from at least one of the first plurality of ring oscillators and/or the second plurality of ring oscillators. Notably, the ring oscillator selection circuit is commonly shared by the PUF and the age sensor circuit. Also, the IC may further include an output function circuit adapted to receive and compare the two ring oscillator outputs and generate an output signal.

Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.

Abstract: A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+1)/2 is an odd number.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.

Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

Abstract: The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied during semiconductor processing to provide a semiconductor die having devices of varied values. In other aspects, different areas of semiconductor dies are exposed during semiconductor processing to provide semiconductor dies with devices that vary in value from one die to the next. For each semiconductor die, a value generated based on the values of the die's respective devices can be associated with that die thereby enabling subsequent authentication of the semiconductor die.

Abstract: An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.

Abstract: Generating a physically a physically unclonable function (“PUF”) circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.

Abstract: Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to a first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node.

Abstract: In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored.

Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.

Abstract: A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.

Abstract: The invention relates to a circuit for generating a true, circuit-specific and time-invariant random binary number, having: a matrix of K?L delay elements that can be connected to each other by means of L?1 single or double commutation circuits into chains of delay elements of length L, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, wherein the setting of the commutation circuits, the demultiplexer, and the multiplexer can be prescribed by a control signal, wherein the circuit comprises a channel code encoder whereby code words of a channel code can be generated and a transcriber, whereby code words of the channel code can be transcribed into the control signal of the L?1 single or double commutation circuits, and a method for generating a true, circuit-specific and time-invariant random number by means of a matrix of L?K delay elements, L?1 single or double commutation circuits, a single or double

Abstract: Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Abstract: A method, non-transitory computer readable medium, and apparatus for preventing accelerated aging of a physically unclonable function (PUF) circuit are disclosed. For example, the method monitors an environmental condition associated with the physically unclonable function circuit, detects a change in the environmental condition associated with the physically unclonable function circuit, and, in response to the change in the environmental condition, implements a security function for preventing the accelerated aging of the physically unclonable function circuit.

Abstract: A functional timing sensor includes a setup time violation detecting circuit, a hold time violation detecting circuit, and an interface from the setup time violation detecting circuit and the hold time violation detecting circuit. The interface provides a notification upon detection of a violation by either the setup time violation detecting circuit or the hold time violation detecting circuit.

Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract: A method and an apparatus for supporting a self-destruction function in a baseband modem are provided. A self-destruction method of a baseband modem includes sending a request for supplying power to a self-destruction unit to a power management unit when a command for performing the self-destruction is received from a base station and controlling the self-destruction unit to output a signal corresponding to a specific bit value. The signal output by the self-destruction unit is used to block a clock supplied from a Temperature-Compensated crystal Oscillator (TCXO) to the baseband modem through a logical operation with a signal output by the TCXO.

Abstract: An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.

Abstract: A current-mode-logic gate designed to have a first electronic path and a second electronic path. Each electronic path has a pair of transistors. The second electronic path is physically separated and identical to the first electronic path. In operation, a first input signal is transmitted through the first electronic path of the current-mode-logic gate to produce a first output signal. Similarly, a second input signal is transmitted through the second electronic path of the current-mode-logic gate to produce a second output signal.

Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: Method, relay node and computer program product for processing transport packets, the transport packets conveying: (i) data stream units forming a data stream, and (ii) correction data units relating to the data stream units, where each transport packet contains information identifying the content of units in that transport packet. Transport packets are received at the relay node, the data stream units in the transport packets received at the relay node being insufficient to constitute the data stream. At least some of the correction data units and the data stream units in the received transport packets are used to generate substitute data stream units thereby to substantially recover the data stream at the relay node. The relay node packetizes the data stream units of the substantially recovered data stream with correction data units to form output transport packets for transmission from the relay node, and then the output transport packets are transmitted from the relay node.