Abstract: A constantly conductive MOS transistor is placed in a logic circuit including a plurality of switching MOS transistors. The switching MOS transistors and the constantly conductive MOS transistor are connected in series and each receive a control signal at their respective gates. The constantly conductive transistor is in a conductive state regardless of the state of its control signal. Thus, it is difficult for a third party to learn the true logic structure of the logic circuit by visual inspection, as the third party will tend to recognize the constantly conductive transistor as a true transistor contributing to the logic circuit, and not as a constantly conductive "dummy" transistor.
Abstract: For a data processing device having a main memory comprised of a non-volatile memory and a CPU, memory protection and security are ensured for its programs and so forth. An auxiliary memory for storing security bit data is provided, for example, in an EPROM that comprises the main memory. Assuming that the result read by the CPU is "0" when a current flows between a drain and a source of a transistor in the EPROM, and "1" when the current does not flow, then the security bit data read from two transistors A and B are A=1 and B=1, which means they are set so that access to the main memory and a write to the auxiliary memory are prohibited. With A=0 and B=0, security is set, but a write to the auxiliary memory is permitted; with A=1 (0) and B=0 (1), security is reset.
Abstract: A plurality of light-receiving devices dispersed over the area of an IC chip operate in response to the opening of an IC device such that switching transistors are turned on or off to prohibit the normal operation of logic circuits or logic elements, thereby securing protection against normal reading of the internal data of the opened IC device, particularly against the analysis of the IC's internal logic with an electron beam tester.
Abstract: A method and apparatus for sequencing an integrated circuit which receives an external clock signal consists of the use of an internally generated random clock signal and of the use of either of these clock signals depending on the instruction to be performed.
Abstract: An SRAM-based programmable logic device having decompression and decryption circuits between its EPROM nonvolatile programming data storage and its SRAM programming registers is secured against copying of the programming data because a would-be copyist would need to know the compression and encryption used. In a system and method for programming the device, a user station preferably contains a plurality of possible encryptions and a plurality of possible compression schemes. An encryption and compression scheme are selected, preferably at random, by the user or by the programming software in the user station. Data indicating which encryption and compression scheme were chosen are included in the programming data to allow decompression and decryption.
Abstract: An SRAM-based programmable logic device having decompression and decryption circuits between its EPROM nonvolatile programming data storage and its SRAM programming registers is secured against copying of the programming data because a would-be copyist would need to know the compression and encryption used. In a system and method for programming the device, a user station preferably contains a plurality of possible encryptions and a plurality of possible compression schemes. An encryption and compression scheme are selected, preferably at random, by the user or by the programming software in the user station. Data indicating which encryption and compression scheme were chosen are included in the programming data to allow decompression and decryption.
Abstract: The Personal Electronic Book System invention replaces a standard handheld book with an electronic equivalent. The invention is sized and configured to be book size and to open like a book for use. When opened, the user sees two facing page-like touch-sensitive, display screens with black print on white background. Icons represent the electronically stored material, "artwork, audio clips, books, E-mail, faxes, games, magazines, movies, musical compositions, newspapers, photographs, software, video clips, etc.", which are selected by touching the icon. When a book, magazine, newspaper, or the like is selected, its table of contents is displayed and the user can then read page by page or go directly to a particular page by touching the selection listed in the table of contents. Closing the Personal Electronic Book automatically shuts down the device.
Abstract: This invention relates to a system for providing programmable configuration protection of a programmable Input/Output device. By configuration protection, it is meant that the programming options of an I/O controller can be set in accordance to a given environment, and then by use of a programming controlled signal, prevent the changing of the programmed environment or remove those programmed options considered unsafe in the now secured environment.
Type:
Grant
Filed:
January 5, 1996
Date of Patent:
November 11, 1997
Assignee:
Packard Bell NEC
Inventors:
Jimmy Dean Smith, Mark D. Nicol, Brian K. Straup, Terence Paul O'Brien, Michael P. Krau, Richard David Ball
Abstract: A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.
Type:
Grant
Filed:
June 30, 1994
Date of Patent:
July 16, 1996
Assignee:
PMC-Sierra, Inc.
Inventors:
Graham B. Smith, Charles K. Huscroft, Vernon R. Little
Abstract: A structure and method for configuring a field programmable gate array (FPGA). A configuration memory cell within the FPGA receives a programming signal. In response, the configuration memory cell provides a signal to a configuration control circuit to configure the FPGA. The configuration memory cell includes an input lead, a storage device and a selectable configuration circuit. The input lead carries the programming signal to the storage device. The storage device stores the programming signal and an inverted programming signal which is the inverse of the programming signal. The selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to a first input lead of the configuration control circuit. The configuration control circuit couples (or decouples) various elements of the FPGA in response to the signal provided on the first input lead.