Abstract: An integrated circuit comprising a processor and memory storing: secret information accessible via a first address, the secret information comprising a string of bit values; an inverse-string accessible via a second address, the inverse-string comprising a string of bit values, wherein each of the bit values in the inverse-string is the logical inverse of a bit value at a corresponding bit position in the secret information, the integrated circuit being programmed with code configured to: (i) receive a request for the secret information; and (ii) test whether the bit-values of the inverse string are the inverse of the bit-values at respective corresponding bit positions of the secret information.

Abstract: An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask. Operating the first component produces an output that is dependent on the dynamic characteristic of the first component. A digital value associated with the integrated circuit is generated using the output of the first component, and then the generated digital value is used in operation of the integrated circuit.

Abstract: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Abstract: A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier from the first component and store the first unique identifier in the one time programming section during the first time initialization. Upon subsequent initializations, the processor may acquire the first unique identifier from the first component and compare the first unique identifier to the stored first unique identifier. The processor may allow the subsequent initializations to proceed if the first unique identifier matches the stored first unique. The processor may disallow the subsequent initializations from proceeding if the first unique identifier does not match the stored first unique identifier.

Abstract: A system for encrypting and decrypting data in a data stream for programming a Field Programmable Gate Array (FPGA). The system allows for an enable bit to be set for a gap in the data stream and the data is then encrypted from the beginning of the gap. A gap being bits in said data stream that correspond to unprogrammed addresses of a memory in the field programmable gate array. The data is then decrypted by the FPGA when the bit stream is received and an enable bit is detected in a gap of the data stream.

Abstract: Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to the memory array. The control circuit may be configured to selectively prevent access to data stored within the memory array upon removal of the memory component from the electronic system. Various additional methods, devices, and systems are also provided.

Abstract: A data processing apparatus having a dual rail circuit component and a control unit for production of drive signals for the dual rail circuit component. The control unit receives an operating mode selection signal, and drive signals for the connected dual rail circuit component are produced as a function of the operating mode selection signal. The circuit components are operated in a security mode or in a power saving mode as a function of the drive signals, with security measures being deactivated in the power saving mode.

Abstract: The semiconductor device of the present invention includes: first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer; a plurality of signal wiring layers formed above the first defensive wiring; and means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.

Abstract: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Abstract: A chip is provided that includes a plurality of on-chip configurable features having a disabled and an enabled state. The on-chip configurable features are each operable to change from the disabled state to the enabled state upon receipt of a valid enablement configuration from an enabling entity. A method for the chip is provided to disable the plurality of on-chip configurable features before delivery of the chip to a new location. The chip is delivered to a new location where a unique hardware identifier and data for at least one of the on-chip configurable features is retrieved. The unique hardware identifier and the data are transmitted to an enabling entity. The enabling entity sends the enablement configuration to the chip. The chip is programmed with the enablement configuration, which enables the at least one on-chip configurable feature at the new location.

Abstract: A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an output node. The logic circuit may be a set dominant latch and a memory circuit may be formed based on the set dominant latch.

Abstract: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Abstract: An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.

Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Abstract: Various techniques for controlling use of configuration data for and/or a design implemented as user logic in a configurable PLD (programmable logic device) include programming the configurable PLD using configuration data provided by a secure device. The programmed configurable PLD includes user logic, a configurable device authorization code generator and a comparator. The user logic is immediately disabled after it is loaded into the configurable device. A configurable device authorization code is generated in the configurable device authorization code generator in the programmed configurable PLD and is sent to the comparator. A secure device authorization code is generated by a secure device authorization code generator and also is sent to the comparator. The comparator compares the two inputs and, if the configurable device authorization code and secure device authorization code are identical, the user logic is then enabled.

Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Abstract: An apparatus for expressing circuit version identification (VID) includes multiple conductive layers, a circuit VID unit, and a first and a second pull-up or pull-down circuits. Each of the conductive layers includes a first and a second conductive line. The first pull-up or pull-down circuit is coupled to the first conductive line. An input terminal of the circuit VID unit is coupled to the second conductive line. An output terminal of the circuit VID unit outputs the circuit VID. The second pull-up or pull-down circuit is coupled to the input terminal of the circuit VID unit. When the circuit VID needs to be in a first state, the first conductive line and the second conductive line are disconnected from each other. On the other hand, when the circuit VID needs to be in a second state, the first conductive line and the second conductive line are coupled to each other.

Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has a determined electrical resistance which is used to monitor the validity of the fence.

Abstract: A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

Abstract: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Abstract: A method of protecting data stored by an electronic device includes determining an identity of a restricted device. Also determined is the identity of restricted data associated with the restricted device, the restricted data being one or more items of data stored by the electronic device. Data protection for the restricted data to limit access to the restricted data by the restricted device in invoked when geographic presence of the restricted device with respect to the electronic device is detected.

Abstract: Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.

Abstract: A physically small, inexpensive to manufacture stand-alone dedicated function drive preparation device connects to a long term storage device such as a hard drive. The drive preparation device performs operations on the storage device such as formatting, copying, verifying, configuring, testing, and cleaning. Additionally the device may be configured set passwords. The device may also be configured to make multiple copies of a source storage device, these copies having unique network identifications. The device may be configured by a user.

Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

Abstract: The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element.

Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.

Abstract: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

Abstract: A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.

Abstract: Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.

Abstract: An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode. A method for controlling access to the port is also provided.

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract: The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace.

Abstract: Methods and structures for design security in configurable devices are described. In some embodiments, a configurable device may be placed in an unsecured mode allowing for access to configuration data and other diagnostic functions during development and production phases. Once the device is finalized, it may be placed in a secure mode that disables a configuration path and enables a bypass path, thereby securing the configuration data. In some embodiments, the configurable device may be a programmable logic device, such as a complex programmable logic device.

Abstract: An apparatus for disabling a circuit when the circuit is in a first preselected condition includes a critical element that has an enable state and a disable state. The critical element is configured in relation to the circuit such that the circuit cannot operate normally if the critical element is in the disable state. A trigger generates a state signal that causes the critical element to enter the disable state when a comparison of a current condition to a stored value indicates that the circuit is in the first preselected condition. In a method of controlling operation of a circuit, a current condition is sensed. Whether the current condition corresponds to a stored value is determined. If the current condition corresponds to the stored value, then a critical element is caused to enter a disable state so that the circuit is prevented from operating normally.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

Abstract: A method, apparatus, and system are provided for extending a trusted computing base (TCB). According to one embodiment, a first level trusted computing base (TCB) is generated having hardware components including a trusted platform module (TPM), and an extended TCB is formed by adding a second level software-based TCB to the first level TCB, and properties associated with the first level TCB are transferred to the second level TCB.

Abstract: A method, system and apparatus for identifying unauthorized access to memory locations in a multi-element data storage device. The invention includes a restrictive key that is physically coupled to at least one inaccessible memory element in the data storage device. The key prevents the user from accessing the data in that element. A securing device connects the restrictive key to the data storage device's housing. When the key is altered from its initial position, the securing device is broken. Because the securing device is at least partially located on the outside of the device housing, it is readily visible. Therefore, if the securing device has been broken, the key to which the securing device was coupled was necessarily moved. This provides visual evidence that there has been an attempt to access one or more data memory areas that had been previously been rendered inaccessible by the restrictive key.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: An example embodiment of the present invention relates to a method of executing a logic operation while remaining safe from side channel attacks. Another example embodiment of the present invention relates to a logic circuit and device for executing a logic operation while remaining safe from side channel attacks.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

Abstract: Methods and structures for protecting programmable logic device (“PLD”) programming files are disclosed. In one respect, an embodiment of the present invention includes applying a particular protective setting to a PLD, the setting has a relationship to proper programming of the PLD. A configuration program generates programming data including a non-pre-processed and a pre-processed portion. The pre-processed data reflects the results of processing that is carried out off-device (e.g. by the configuration program on a user computer), but is consistent with the logic of certain on-device processing circuitry. The pre-processing also takes into account information regarding the particular applied setting. The non-pre-processed portion of the programming data is further processed by the certain on-device processing circuitry. The output of the on-device processing circuitry is combined with the pre-processed portion of the programming data in a bit stream for programming the PLD.

Abstract: A copy protection circuit to prevent illegal copy of a circuit configuration data when the user circuit data is read out and transferred from a storage device to a rewritable gate array (FPGA), includes a control circuit, a data generating circuit and a data switch circuit. The control circuit controls transfer of the circuit configuration data from the storage device to the FPGA, and the data generating circuit generates pseudo circuit configuration data. The data switch circuit transfers to the FPGA, the circuit configuration data read out from the storage circuit and the pseudo circuit configuration data outputted from the data generating circuit. The data switch circuit transfers to the FPGA the circuit configuration data which is less than a data amount that the FPGA needs, and then the pseudo circuit configuration data.

Abstract: A configurable circuit that includes configuration data protection features, and related methods, are described herein.