Abstract: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Abstract: An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar transistor, or to design a circuit having this property. If the component is stressed due to the presence of this circuit, it is immediately deactivated, actually preventing the revelation of the secrets thereof.

Abstract: A method and a circuit for protecting at least one piece of information contained in an electronic circuit by disabling at least one function of the circuit in case of detection of a number of abnormal operations greater than a threshold, in which the disabling of the function is temporary, of a duration independent from whether the circuit is powered or not.

Abstract: A method and a circuit for protecting data contained in an electronic circuit against a disturbance of its operation, in which a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered.

Abstract: In a program execution method in which a program to be executed is stored in a central unit and a terminal unit acquires the program from the central unit and executes the program, when the central unit receives an acquisition request from the terminal unit, it creates a load module different from the program, which produces the same computation results and differs in the location where essential information is to be embedded, and transmits the load module to the terminal unit together with the essential information necessary for executing the program. The terminal unit receives the program, stores the program on a memory, and executes the program based on the embedded essential information. This method makes it difficult for malicious third parties to illegally execute the program by reverse analysis, and enhances the security of the load module to be executed.

Abstract: In one embodiment, a database access system includes a remote client application, a database having a plurality of data records, and a data event agent. The database has a plurality of data records and is coupled to the data event agent. The data event agent is remotely coupled to the remote client application through a firewall and operable to receive a query from the remote client application. In response to receipt of the query, the data event agent stores the query in memory in order to continually filter additions and modifications to data records against the one or more filter criteria included in the query. In the event that a data record matches the query, the data event agent transmits the data record to the remote client application.

Abstract: An electrical device having a logic gate whose consumption is independent from its input data and its logic state. To this end, the device uses logic means forming switches. The interest in having a device of this type is, for example, to protect chip cards and other cryptosystems from attacks via auxiliary channels, such as collision attacks by and attacks by differential analysis of current, power or consumption. This protection is provided by the hardware. The device is for integration in all devices requiring such a protection.

Abstract: The present invention relates to an apparatus and method for easily, quickly and permanently decommissioning an electronic data storage device by thoroughly exposing the device to a strong field of microwave energy thereby eliminating any possibility of retrieving data from the device. The magnetron is operated as peak power and pulsed for the time needed to assure data destruction.

Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.

Abstract: A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.

Abstract: In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.

Abstract: Techniques are provided for reducing the likelihood of piracy of integrated circuit design using combinational circuit locking system and activation protocol based on public-key cryptography. Every integrated circuit is to be activated with an external key, which can only be generated by an authenticator, such as the circuit designer. During circuit design, register transfer level (RTL) descriptions of the IC design are embedded with combinational logic based on a master key applied by the authenticator. That combinational logic renders at least one module of the RTL description locked, i.e., encrypted. The completed circuit design from the authenticator is sent to a fabrication lab with the combinationally locked modules. After fabrication, the circuit can only be activated when the authenticator sends an appropriate key that is used by the circuit to unlock the locked portions and thereby activate the circuit.

Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.

Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.

Abstract: A semiconductor integrated circuit device includes: an inter-equipment authentication section formed on a chip and configured to perform inter-equipment authentication between the inter-equipment authentication section itself and source equipment; a control section formed on the chip and configured to control the inter-equipment authentication, the control section operating when a system clock from an oscillation section is supplied, and being capable of giving instructions to stop the oscillation of the oscillation section; and an oscillation stop canceling section configured to output an oscillation stop canceling signal to restart the oscillation of the oscillation section, based upon whether or not 5 volts of DDC from the source equipment is supplied to an input terminal. The start of the operation of a microcontroller unit on a system on chip is cable of being controlled by the 5 volts of DDC, which are power supply voltage supplied from the source equipment via DDCs.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: An integrated circuit can be made more secure by programming a one time programmable circuit so that different signals are provided on terminals as compared to when the integrated circuit was not secure. Instead, or in addition, the integrated circuit can be made more secure by providing decode circuitry that can be used with the one time programmable circuit to select different internal address maps in response to an address value. The decode circuitry can use a first address map when the integrated circuit is secure, and a different address map when the integrated circuit is non-secure.

Abstract: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Abstract: Systems and methods for enabling on-chip features via efuses. A system comprises an electronic fuse (Efuse) array (EFA) coupled to each features capability register (FCR) within an instantiated computational block. The EFA comprises a plurality of rows wherein programming an row comprises blowing one or more Efuses of the row. A valid row comprises programmed Efuses corresponding to one or more on-chip enabled features. The EFA is further configured to prevent enabling of disabled on-chip features from occurring subsequent to a predetermined point in time, such as the time of shipping the chip to the field for use by end-users, by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the EFA. In one embodiment, some features correspond to on-chip hardware cryptographic acceleration.

Abstract: A method for configuring a chip having a plurality of on-chip configurable features. The plurality of on-chip configurable features is disabled before delivery of the chip to a new location. The chip is delivered to a new location where a unique hardware identifier and data for at least one of the on-chip configurable features is retrieved. The unique hardware identifier and the data are transmitted to an enabling entity. The enabling entity sends the enablement configuration to the chip. The chip is programmed with the enablement configuration, which enables the at least one on-chip configurable feature at the new location.

Abstract: Provided is a logic circuit comprising a metal-insulator transition (MIT) device, including: an MIT device unit including an MIT thin film, an electrode thin film contacting the MIT thin film, and at least one MIT device undergoing a discontinuous MIT at a transition voltage VT; a power source unit including at least one power source applying power to the MIT device; and at least one resistor connected to the MIT device, wherein a logic operation is performed on a signal through the power source to output the result of the logic operation as an output signal.

Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.

Abstract: An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact.

Abstract: A method of verifying configuration data to be loaded into a device having programmable logic is described. The method comprising the steps of validating a configuration bitstream to be loaded into the device having programmable logic; storing a validation indicator with the configuration bitstream in a non-volatile memory device; and configuring the programmable logic according to the configuration bitstream if the validation indicator indicates that valid data is stored in the non-volatile memory device. A system for verifying configuration data to be loaded into a device having programmable logic is also described.

Abstract: A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Abstract: An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device.

Abstract: A device having protection capabilities, the device includes a voltage supply unit that is connected to an integrated circuit and provides a supply voltage to the integrated circuit; wherein the integrated circuit includes: a security real time clock generator that includes an input; a masking unit that is connected to the input, wherein the masking unit isolates the input when a voltage supply monitor is disabled; and wherein the voltage supply monitor monitors the voltage supply unit and wherein a change in a level of supply voltage affects a level of a signal provided to the input.

Abstract: The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device.

Abstract: A method and eFuse circuit for implementing enhanced security features using eFuses, such as disabling selected predefined test, debug, and mission security functions used in application-specific integrated circuits (ASICs), and a design structure on which the subject circuit resides are provided. The eFuse circuit includes a plurality of eFuses, a sense amplifier coupled to the plurality of eFuses, and a plurality of sense output latches coupled to the sense amplifier. The plurality of sense output latches is arranged to have a bias to power up to a known value. Control logic coupled to the plurality of sense output latches provides at least one predefined control signal responsive to the known value of the plurality of sense output latches, which enables a selected predefined security function. The plurality of eFuses is sensed and the ASIC is configured to a predefined state responsive to an applied POR/Sense control signal.

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract: An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact.

Abstract: Processing components to manufacture information handling systems have build-to-order integrated circuits with plural selectively-enabled features set at the information handling system manufacture location. For instance, fuses integrated in the integrated circuits are selectively blown at the information handling system manufacture location to permanently disable features so that the processing components have a desired configuration. As another example, feature enable or disable states are programmed in flash incorporated in the integrated circuit, with the flash programmability subsequently disabled to permanently set the features so that the processing components have a desired configuration. Features are set with keys provided by the processing component manufacturer to track the information handling system manufacturer's use of the features.

Abstract: A system implements and authorizes use of a user design. A non-volatile memory stores combined configuration data including first configuration data for implementing a user design and an authorization module, and second configuration data for implementing a generator of a check code. In response to a reset, a programmable integrated circuit loads the first configuration data to implement the user design and the authorization module. The implemented authorization module generates an activation code from an identifier when the check code is available from the non-volatile memory and enables the user design when the check and activation codes match. The programmable integrated circuit loads the second configuration data to implement the generator when the check code is not available from the non-volatile memory. The implemented generator erases the second configuration data from the non-volatile memory, generates the check code from the identifier, and stores the check code in the non-volatile memory.

Abstract: Systems and methods are disclosed herein to provide improved security key techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a method of providing data security for a programmable logic device (PLD) includes programming a plurality of programmable fuses that stores a security key comprising a plurality of data bit values, wherein each data bit value is associated with a respective subset of at least three of the fuses. The security key is retrieved from the fuses using the data bit values stored by each subset of the fuses. An encrypted configuration data bitstream is decrypted using the retrieved security key to obtain an original configuration data bitstream to configure the PLD.

Abstract: Methods, systems, apparatuses and products are disclosed for providing security circuits. Exemplary embodiments including semiconductor chips on circuit boards are shown, together with application in a movie stick/movie player pair. Such systems provide for and improve on the means for clocked logic security support beyond what is available in current security products while being capable of embodiment in low cost technologies such as programmable gate arrays.

Abstract: The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device.

Abstract: An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects.

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract: In some embodiments an indication of an intended use of a logic device is stored in a register of the logic device, and any further programming of the register is prevented. Other embodiments are described and claimed.

Abstract: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.

Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Abstract: The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.

Abstract: The invention relates to a logic gate whose consumption is independent from its input data and its logic state. To this end, the device uses logic means forming switches (220, 720, 750). The interest in having a device of this type is, for example, to protect chip cards and other cryptosystems from attacks via auxiliary channels such as collision attacks by and attacks by differential analysis of current, power or consumption. This protection is provided by the hardware. The invention is for integration in all devices requiring such a protection.

Abstract: The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace.

Abstract: An integrated circuit is provided having a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit position in the first string, and a processor configured to test whether the bit values of the second string are the inverse of the bit values at respective corresponding bit positions of the first string by combining the corresponding bits of the first and second strings.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.