Synthesizer Patents (Class 327/105)
  • Patent number: 10958278
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Ariel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
  • Patent number: 10958255
    Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Gil Asa, Assaf Ben-Bassat, Ofir Degani, Shahar Gross, Rotem Banin, Uri Grosglik
  • Patent number: 10879845
    Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagalinga Swamy Basayya Aremallapur, Sriram Murali, Jawaharlal Tangudu
  • Patent number: 10848161
    Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 24, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Reuben P. Nelson
  • Patent number: 10839865
    Abstract: Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventors: Amit Chhabra, Saikat Kumar Banik
  • Patent number: 10819353
    Abstract: A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 27, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy A. Monk, Douglas F. Pastorello
  • Patent number: 10749504
    Abstract: A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 18, 2020
    Assignee: NEWCOSEMI (BEIJING) TECHNOLOGY CO., LTD.
    Inventors: Deyi Pi, Chang Liu
  • Patent number: 10749368
    Abstract: A method of operating a computer mouse includes receiving electromagnetic (EM) radiation emitted from a source external to the computer mouse, the received EM radiation induces noise within one or more bands of noise frequencies and an image sensor circuit of the computer mouse generates erroneous movement detection signals in response to an operating frequency of the image sensor circuit being within the one or more bands of noise frequencies. The method further includes determining the operating frequency of the image sensor circuit, comparing the operating frequency to a target frequency, wherein the target frequency is outside of the one or more bands of noise frequencies, and tuning the operating frequency of the image sensor circuit towards the target frequency.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 18, 2020
    Assignee: Logitech Europe S.A.
    Inventors: François Morier, Laurent Plancherel, Florian Jeannerat, Jean Salathé, Hugues Favey, Frédéric Fortin, Fabrice Sauterel
  • Patent number: 10749537
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang, Ruey-Bin Sheen, Cheng-Hsiang Hsieh
  • Patent number: 10733032
    Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: John Divirgilio, Liana L. Fong, John Lewars, Seetharami R. Seelam, Brian F. Veale
  • Patent number: 10720887
    Abstract: Superconducting device applications implemented with a surface acoustic wave resonator and a superconducting microwave resonator coupled to a Josephson ring modulator are provided. A method can comprise receiving, by a microwave Josephson mixer, and from a superconducting surface acoustic wave resonator of a superconducting device, a surface acoustic wave signal that comprises one or more phonons that resonate at a first frequency. The method can also comprise receiving, by the microwave Josephson mixer and from a superconducting microwave resonator of the superconducting device, a microwave signal that comprises one or more photons that can resonate at a second frequency. Further, the method can also comprise mixing, by the microwave Josephson mixer, the surface acoustic wave signal and the microwave signal based on a microwave control signal received from a microwave source operatively coupled to the microwave Josephson mixer.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10715157
    Abstract: A mobile communication device adapted to perform spur relocation for a digital phase-locked loop includes a receiver to determine a first frequency channel of interest and to identify a first frequency command word corresponding to the first frequency channel of interest. The mobile communication device further includes control logic circuitry to identify a first frequency at which a first fractional spur associated with the first frequency command word starts to occur and to determine whether the identified first frequency is within the first frequency channel of interest. In addition, the mobile communication device includes a programmable feedback divider configured to change the first frequency command word to a second frequency command word, wherein a second fractional spur associated with the second frequency command word occurs at a second frequency outside the first frequency channel of interest.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Basak Can, Balvinder S. Bisla
  • Patent number: 10693446
    Abstract: Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: June 23, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chien-Wen Chen
  • Patent number: 10693488
    Abstract: A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2n?(2m?1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2n+(2m?1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n?m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 23, 2020
    Assignee: DENSO CORPORATION
    Inventor: Takamoto Watanabe
  • Patent number: 10686458
    Abstract: A TAF-DPS based circuits and methods to improve electronic system's frequency accuracy and enhance its frequency stability is disclosed in this application. Present invention creates a circuit architecture and a calculation scheme for compensating frequency source's frequency error. Present invention further discloses a method of incorporating said scheme into functional chip built in either ASIC or FPGA fashion. Present invention further presents a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance from the time synchronization perspective.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 16, 2020
    Inventor: Liming Xiu
  • Patent number: 10659062
    Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 19, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Yanagihara, Koji Tsutsumi, Mitsuhiro Shimozawa
  • Patent number: 10652065
    Abstract: Systems, methods, and devices are provided for correcting compression distortion of wireless signals due to variations in operation parameters of the radio frequency system. The method may include using circuitry to generate a reference signal that is not pre-distorted by a processing block. The method may involve receiving an envelope signal representative of a signal being transmitted by a transceiver. The method may also involve determining a first peak-to-average ratio of the envelope signal and receiving a second peak-to-average ratio of the reference signal. The method may additionally involve determining a difference between the first peak-to-average ratio and the second peak-to-average ratio. The method may also include adjusting a gain of an amplifier of the transceiver based on the difference.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Ioannis Sarkas, Berke Cetinoneri, Qishan Yu
  • Patent number: 10622946
    Abstract: A radio frequency (RF) mixer is provided. The RF mixer includes two linear-in-the-amplitude-domain RF channels connected in parallel, with each of the two linear-in-the-amplitude-domain RF channels having of an input RF signal applied equally to each channel. Two controllable gain devices are structured to receive the input RF signal. A local oscillator (LO) communicates with both of the controllable gain devices, with one of the controllable gain devices receiving a signal from the LO directly, and the other controllable gain device receiving a signal from the LO after a phase of the LO signal is reversed by a phase inverter. Finally, an output of each of the linear-in-the-amplitude-domain RF channels is combined to form a common intermediate frequency (IF) output.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Inventor: Sam Belkin
  • Patent number: 10571437
    Abstract: Operational configuration and temperature compensation methods are provided for bulk acoustic wave (BAW) resonator devices suitable for operating with liquids. Temperature compensation methods dispense with a need for temperature sensing, instead utilizing a relationship between (i) change in frequency of a BAW resonator at a phase with adequate sensitivity and (ii) change in frequency of a phase that is correlated to temperature. Operational configuration methods include determination of an initial phase response of a BAW resonator in which temperature coefficient of frequency is zero, followed by comparison of sensitivity to a level of detection threshold for a phenomenon of interest.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 25, 2020
    Assignee: QORVO US, INC.
    Inventors: Rick Morton, Kevin McCarron
  • Patent number: 10536307
    Abstract: At least one embodiment relates to generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF signal is modulated based on the digital baseband signal. Pulses of the pulse sequence are quantized based on a time grid of a third clock rate. A ratio between a number of second clock cycles corresponding to one first clock cycle and a number of third clock cycles corresponding to one first clock cycle is non-integer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 14, 2020
    Assignee: Alcatel Lucent
    Inventors: Daniel Markert, Yu Xin
  • Patent number: 10523221
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang, Ruey-Bin Sheen, Cheng-Hsiang Hsieh
  • Patent number: 10511315
    Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 17, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Vivek Sarda
  • Patent number: 10511311
    Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventor: Stefan Tertinek
  • Patent number: 10483697
    Abstract: An electrical connector includes: an insulative housing; and an inserting module positioned in the insulative housing and including a transformer, the transformer comprising: a magnetic core having a central opening; and a first and second wire groups each including plural wires, each wire having a central portion, a first end, and an opposite second end, the central portions of each wire group wound around the magnetic core through the central opening, wherein the first and second wire groups joint to function as a primary winding and a secondary winding of the transformer, and a wire diameter of the secondary winding is greater than a wire diameter of the primary winding.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 19, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Yong-Chun Xu, Chih-Ching Hsu
  • Patent number: 10484748
    Abstract: Upstream noise suppression circuits include a splitter and a combiner that are connected by first and second communications paths. An information signal removal circuit is provided on the second communications path and is configured to remove an upstream information signal therefrom. A phase shifter is also provided on the second communications path between the upstream information signal removal circuit and the combiner.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 19, 2019
    Assignee: CommScope, Inc.
    Inventor: Mark E. Alrutz
  • Patent number: 10484027
    Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Debesh Bhatta, Deping Huang, Jeffrey Mark Hinrichs
  • Patent number: 10454665
    Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shunta Iguchi, Ilker Deligoz, Michael Naone Farias
  • Patent number: 10411745
    Abstract: According to one embodiment, a radio frequency (RF) receiver circuit includes a low noise amplifier, a poly-phase filter, and an in-phase quadrature (IQ) mixer circuit coupled between the low noise amplifier and the poly-phase filter. The IQ mixer circuit includes an IQ generator having a differential in-phase input port, a differential in-phase output port, and a differential quadrature output port; a first frequency mixer having a differential local oscillator (LO) input port, where the differential LO input port of the first frequency mixer are coupled to the differential in-phase output port of the IQ generator to drive the first frequency mixer; and a second frequency mixer having a differential LO port, where the differential LO input port of the second frequency mixer are coupled to the differential quadrature output port of the IQ generator to drive the second frequency mixer.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 10, 2019
    Assignee: SPEEDLINK TECHNOLOGY INC.
    Inventors: Min-Yu Huang, Hua Wang, Thomas Chen, Taiyun Chi
  • Patent number: 10411715
    Abstract: A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral temperature, and a controller that is electrically connected to the oscillator and that corrects temperature dependent error in the oscillation frequency of the oscillator based on the temperature detected by the temperature sensor and a sealing member that integrally seals the oscillator and the semiconductor integrated circuit.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 10, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kazuya Yamada, Toshihisa Sone, Akihiro Takei, Yuichi Yoshida, Kengo Takemasa
  • Patent number: 10404260
    Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 3, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Sangeetha Gopalakrishnan, Sheng Ye, Vamsi Paidi, Raghava Manas Bachu
  • Patent number: 10359829
    Abstract: It is to provide a technique capable of controlling the throughput and the power consumption of a semiconductor device at a desired ratio. A semiconductor device includes a clock generation circuit that generates a clock signal and a data processing unit that receives the clock signal. The clock generation circuit includes an oscillator that generates a source clock signal, an output circuit that outputs a clock signal with the source clock signal enabled, and a control circuit having a setting circuit in which the data processing unit sets the ratio of the enable. The semiconductor device can change the frequency of the clock signal by partially permitting or prohibiting the source clock signal in time.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoki Mitsuishi
  • Patent number: 10345376
    Abstract: A binary signal generator circuit includes a programmable waveform generator (PWG) having an input stage for receiving a digital data stream, a serial clock signal for controlling receipt of the digital data, a frequency synchronization and a clock signal. The PWG includes registers including a first and second register for storing bits representing a first frequency (f1) and for storing bits representing a zero frequency (fo), respectively. A MUX receives a control signal based on the digital data for toggling between bits representing f1 and fo coupled to a digital-to-analog converter (DAC) with an output providing a modulated signal that toggles between essentially f1 and essentially fo. A differential output amplifier receives the modulated signal for generating a first and second amplified signal modulated between essentially f1 and essentially fo. The first and second amplified signal are phase shifted relative to one another, taken together providing a differential signal.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kui Ting Soo, Michael Cayanan Ramirez
  • Patent number: 10340122
    Abstract: Systems and methods for controlling a process applied to a substrate within a plasma chamber are described. The systems and methods include generating and supplying odd harmonic signals and summing the odd harmonic signals to generate an added signal. The added signal is supplied to an electrode within the plasma chamber for processing the substrate. The use of odd harmonic signals facilitates high aspect ratio etching of the substrate.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: July 2, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhigang Chen, Alexei Marakhtanov, John Patrick Holland
  • Patent number: 10296228
    Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. Each hard drive sub-board is coupled to one or more expanders, via and interface unit, with a set of dual-pass shielded cables. The expander includes a plurality of chipsets coupled to a complex logic device. Each chipset may communicate with a different subset of hard drives with potentially different timing characteristics. The dual-pass shielded cables may be arranged to mitigate these differences. In addition, pin assignments associated with the cables may be set in order to further mitigate the timing differences.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 21, 2019
    Assignee: SUPER MICRO COMPUTER, INC.
    Inventors: Kelvin Tseng, Trina Shih, Lawrence H. Liang, Richard Chen
  • Patent number: 10277235
    Abstract: A fine-adjustment synthesizer includes a fractional phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a mixer, a baud-pass filter, and a feedback path programmable fractional frequency divider. A coarse-adjustment synthesizer includes an integer-type phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a band-pass filter, and a feedback path programmable integer frequency divider. An output of a reference signal source is input in parallel to both the fine-adjustment synthesizer and the coarse-adjustment synthesizer. An output of the frequency variable oscillator in the fine-adjustment synthesizer and an output of the frequency variable oscillator in the coarse-adjustment synthesizer are guided to the mixer and an output signal of the fine-adjustment synthesizer is guided to an output end.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 30, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhisa Yamauchi, Nobuhiro Tokumori, Kenji Miyasaka, Takashi Fujiwara, Masaki Kawamura
  • Patent number: 10164649
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10164646
    Abstract: A frequency generator includes: a PLL circuit, arranged to generate a first output clock and a first lock signal, the first output clock being generated based on an input clock, the first lock signal being used to indicate whether the first PLL circuit is locked, wherein when the first PLL circuit is locked, a frequency of the first output clock is N1 times a frequency of the input clock, and N1 is a positive integer; and a second PLL circuit, arranged to generate a second output clock and a second lock signal, the second output clock being generated based on the input clock, the second lock signal being used to indicate whether the second PLL circuit is locked, wherein when the second PLL circuit is locked, a frequency of the second output clock is N2 times the frequency of the input clock.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 10158366
    Abstract: A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 18, 2018
    Assignee: The Regents of the University of California
    Inventors: Ian Galton, Colin Weltin-Wu
  • Patent number: 10128747
    Abstract: Voltage source circuits, asynchronous processing systems and methods are disclosed. A voltage source circuit includes a capacitor storing an operating voltage for an asynchronous processor. A frequency comparator compares a frequency reference and a feedback signal indicative of an operating frequency of the asynchronous processor to determine whether or not the operating frequency is less than a target frequency. When operating frequency is less than the target frequency, a charge pump adds charge to the capacitor.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 13, 2018
    Assignee: Eta Compute, Inc.
    Inventor: Paul Murtagh
  • Patent number: 10097179
    Abstract: A mixing module (40) comprises a switching mixer (400), controlled by a switch signal and configured to receive an inputting signal and generate an outputting signal; a modulating unit (402), coupled to the switching mixer (400) and configured to generate the switch signal; wherein a switching frequency of the switch signal is higher than an and is a specific multiple of inputting frequency of the inputting signal. The mixing module (40) controls the switching mixer (400) by using the switch signal which is much higher than the inputting frequency of the inputting signal; oversampling is performed on the inputting signal, so that the spectrum energy of the outputting signal is more concentrated, which can avoid the additional noise due to the introduction of sidelobes or harmonics.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 9, 2018
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Fu-Chiang Yang, Yingsi Liang
  • Patent number: 10090992
    Abstract: A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 2, 2018
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Robert Polster, José-Luis Gonzalez Jimenez, Ivan Miro Panades
  • Patent number: 10079557
    Abstract: System and apparatus for power conversion. In one embodiment, the apparatus comprising a DC stage, comprising a resonant circuit, for generating a high-frequency resonant current; and an AC stage for converting a high-frequency current, generated from the high-frequency resonant current, to an AC output current, wherein the AC stage comprises: a pair of serially-connected switches for (i) passing, during a first half of a cycle of an AC line, a positive portion of the high-frequency current, and (ii) passing, during a second half of the cycle of the AC line, a negative portion of the high-frequency current; and an unfurling bridge for unfurling a current waveform, formed from the positive and the negative portions, to generate the AC output current, wherein the unfurling bridge is operated at a frequency on the order of three orders of magnitude lower than an operating frequency of the serially-connected switches.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 18, 2018
    Assignee: Enphase Energy, Inc.
    Inventor: Donald Richard Zimmanck
  • Patent number: 10042407
    Abstract: A power supply system includes a power converter configured to generate a high-frequency power signal and connected to a load to supply a plasma process or a gas laser process with power. The power converter has at least one amplifier path including at least one amplifier, an analog signal generated from a digital signal by a digital-analog converter (DAC) being supplied to the amplifier path, and a logic circuit unit configured to generate the digital signal and connected upstream of the DAC. The logic circuit unit has a signal data memory for storing signal data values for generating an analog signal form, an amplitude data memory for storing amplitude data values for influencing amplitudes of the analog signals, and a multiplier for multiplying the signal data values by the amplitude data values. The power converter includes an adjustable voltage supply for supplying the amplifier with a voltage.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 7, 2018
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Daniel Krausse, Anton Labanc, Christian Thome, Alberto Pena Vidal
  • Patent number: 10031169
    Abstract: The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Manthena Vamshi, Jong-Woo Lee, Thomas Byunghak Cho, Byung-Ki Han
  • Patent number: 10026592
    Abstract: Systems and methods for controlling a process applied to a substrate within a plasma chamber are described. The systems and methods include generating and supplying odd harmonic signals and summing the odd harmonic signals to generate an added signal. The added signal is supplied to an electrode within the plasma chamber for processing the substrate. The use of odd harmonic signals facilitates high aspect ratio etching of the substrate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 17, 2018
    Assignee: Lam Research Corporation
    Inventors: Zhigang Chen, Alexei Marakhtanov, John Patrick Holland
  • Patent number: 10027470
    Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Amir Laufer, Itamar Levin, Kevan A. Lillie
  • Patent number: 10013018
    Abstract: A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave acco
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 3, 2018
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Guangyao Wang
  • Patent number: 10003374
    Abstract: A wireless radio frequency transceiver system for Internet of Things includes: a wireless radio frequency transmission module and a wireless radio frequency receiving module. The wireless radio frequency transmission module is used to shape signal waveform of digital signals from the Internet of Things to modulate the digital signals to form modulated output signals, and adopt a self-mixing technique to increase voltage/current amplitude of the modulated output signals and reduce phase noise. The wireless radio frequency transmission module is further used to adopt a current reuse technique to amplify the voltage/current amplitude of the modulated output signals, and transmit the amplified modulated output signals through a first antenna to a wireless channel. The wireless radio frequency receiving module is used to detect carrier input signals received from a second antenna to obtain baseband signals and demodulate the baseband signals to form differential signals.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 19, 2018
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Shuenn-Yuh Lee, Ching-Fu Tsou
  • Patent number: 9992756
    Abstract: Methods and apparatus which allow a wireless terminal (302) to simultaneously maintain connections with multiple base stations (304, 306) are described. Each wireless terminal (302) is capable of supporting multiple separate timing and/or other control loops one, for each base station connection thereby allowing the connections to operate independently and in parallel. Different control signals and/or data are transmitted on each connection that is established with a base station (302, 306). In this manner base stations (302, 306) receive different data allowing for asynchronous data transmission. The data received by the base stations (302, 306) can be supplied to a wired asynchronous network (308) without the need to combine the received data prior to supplying it to the wired network (308). The communications techniques of the invention can be used to implement soft handoffs without the need to duplicate data transmissions to multiple base stations.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Junyi Li, Rajiv Laroia, Mathew Scott Corson
  • Patent number: 9906230
    Abstract: The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 27, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dmitry Petrov, Haitao Mei