Abstract: According to one embodiment, a current source circuit comprises a first circuit, a second circuit, and a current synthesizing circuit. The first circuit generates a first current having a positive temperature characteristic. The second circuit includes a feedback circuit configured to receive a first voltage having a negative temperature characteristic, and output a second voltage equal to the first voltage, and generates a second current having the negative temperature characteristic based on the second voltage. The current synthesizing circuit generates a constant current having an arbitrary temperature characteristic by adding the first and second currents.

Abstract: Method and system for direct conversion receiver (100), transmitter (200), or transceiver (300) device. The device includes a single frequency synthesizer (102) generating a frequency synthesizer output signal. At least one frequency divider (110n) is provided for generating a reduced frequency signal by selectively dividing the single frequency synthesizer output signal by an integer divisor value. Significantly, the device is configured to vary the reduced frequency signal so as to include every frequency the direct conversion communication device is designed to receive within a plurality of frequency bands by adjusting a frequency of the single synthesizer output signal and the divisor value.

Abstract: Very low phase noise radio frequency (RF) source having multiple discrete frequency outputs used, for example, to calibrate phase noise measurement systems. The calibrator output frequencies can be tailored for a particular application using a scalable architecture.

Abstract: A repeater device that is placed between a transmission device connected to a server device and a reception device connected to a console device that controls the server device. The repeater device repeats a signal between the transmission device and the reception device, and includes an equalizer amplifier that amplifies a signal that is received from the transmission device or another repeater device.

Abstract: A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor.

Abstract: An optical path is configured to propagate an input optical signal. A plurality of electrodes are configured to produce a plurality of discrete phase shifts on the optical signal. An output optical signal is phase-shifted with respect to the input optical signal by a sum of the plurality of discrete phase shifts.

Abstract: A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit.

Abstract: The present invention relates to a frequency synthesizer comprising: a reference signal source that provide a first reference signal, a frequency signal generation unit that generates a synthesized frequency output signal at a predetermined frequency, a mixing unit that mixes said synthesized frequency output signal with a frequency tuning signal and outputs a mixer signal, a frequency tuning unit that provides said frequency tuning signal, said frequency tuning unit comprising a first frequency tuning sub-unit and a second frequency tuning sub-unit which alternately provide said frequency tuning signal, wherein, while one of the first and second frequency tuning sub-units is providing the frequency tuning signal, the other of the first and second frequency tuning sub-units is preparing for providing the frequency tuning signal, and a frequency selection unit that selects a desired frequency range from said mixer signal and outputs a frequency synthesizer output signal.

Abstract: Transmitter device which includes at least: a) one delay line designed to output M signals which are delayed in relation to each other, where M is an integer greater than 1; b) a memory, designed to store at least M digital samples of a waveform, where each digital sample contains N bits, and to output each of the M digital samples successively on N output lines respectively under the control of one of the M delayed signals; and c) a digital-analog converter which includes N inputs linked to N output lines, designed to convert the M digital samples received as input from the N output lines of the memory and to successively output, on an output of the digital-analog converter, each of the M analog converted digital samples which together form an analog signal which is representative of the waveform.

Abstract: Embodiments of the present invention include methods for wide bandwidth synthesizer circuits and methods. In one embodiment, the present invention includes a frequency synthesizer comprising a multiplexer and a band group selector. The multiplexer is coupled to receive a plurality of sinusoidal signals. Each sinusoidal signal has a unique frequency. The band group selector selects between a plurality of band groups. The band group selector is coupled to receive a first signal from the multiplexer. The multiplexer multiplexes between the plurality of sinusoidal signals and provides the first signal. The band group selector includes a band mixer. The band mixer mixes the first signal with a band signal having a band frequency. The band signal corresponds to a band group selected from the plurality of band groups. The band group selector provides a transmitter mixer signal and a receiver mixer signal.

Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed.

Abstract: The invention provides a dual-mode voltage-controlled oscillator (DMVCO), a frequency synthesizer and a wireless receiving device, and pertains to the technical field of integrated circuit of radio frequency wireless receiver. The DMVCO and the frequency synthesizer can operate in a wideband mode and a quadrature mode. When operating in the quadrature mode, a quadrature signal is provided for a Single Sideband Mixer of the frequency synthesizer by a quadrature coupling of a first voltage-controlled oscillator unit and a second voltage-controlled oscillator unit in the DMVCO in the overlapped frequency band so that the frequency synthesizer can cover a higher output frequency band. Therefore, the tuning range of the DMVCO of the invention is wide, and the frequency synthesizer using the DMVCO is low in power consumption, simple in structure and has good frequency spur performance.

Abstract: A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period control word and generates a phase selection signal. The delay line unit generates an output clock based on the phase selection signal. The delta-sigma modulator performs a carry-in operation based on a base number and the base number is adjustable and determined by a calibration process of the delay line unit.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A method of automating a process for controlling a voltage waveform applied to an object is provided. A first waveform for applying to the object is received. A first FFT of the first waveform is calculated. A second waveform for input to the waveform generator is determined based on the first waveform. The determined second waveform is sent to a waveform generator. A third waveform is received that is measured across the object based on a waveform generated by the waveform generator. A second FFT of the received third waveform is calculated. The third waveform is compared with the first waveform to determine a convergence status of the third waveform. If the determined convergence status is not converged, an updated waveform is calculated based on the first FFT and the second FFT and the process is repeated with the updated waveform as the determined second waveform.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

Abstract: Provided are a multi-output oscillator using a single oscillator, and a method of generating multiple outputs. The multi-output oscillator includes: an oscillator outputting the single frequency; a multiplier multiplying the single frequency to output a first frequency; a first frequency divider dividing the single frequency by a first division factor; a first mixer outputting a second frequency by mixing an output of the first frequency divider and an output of the multiplier; a second frequency divider dividing the single frequency by a second division factor; a second mixer mixing the output of the second frequency divider and the output of the first mixer to output a third frequency; and a third mixer mixing the output of the second frequency divider and the output of the multiplier to output a fourth frequency.

Abstract: A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Abstract: Present software-defined radios (SDR) employ front end circuits that contain multiple receivers and transmitters for each band of interest, which is inflexible, expensive and power inefficient. A programmable front end circuit is implemented on a CMOS device and is configurable to transmit and receive signals in a wide band of frequencies, thereby providing an adaptable transmitter and receiver operable with current and future wireless networking technologies.

Abstract: A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Abstract: An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit.

Abstract: Time-to-digital converter arrangements and corresponding methods as well as applications thereof are described. The time-to-digital converter in a first mode is coupled with a calibration signal generator and in a second mode is coupled with signal input.

Abstract: A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide an interpolated oscillator control signal at the data output. An interpolation rate of the interpolator may depend on the oscillator control signal. Alternatively, a device can include a digitally controlled oscillator having a control input, a sampling unit coupled to the control input of the digitally controlled oscillator, and a timing error detector coupled to an output of the digitally controlled oscillator. The sampling rate of the sampling unit can depend on an output of the timing error detector.

Abstract: A portable frequency synthesizer is provided with fine tuning over a broad bandwidth using a Fractional N type Delta Sum Phase Locked Loop circuit that enables elimination of boundary value spurs. In the system, frequencies where spurs occur are calculated to define a region of fractional N values that cannot be used with a first time base. To avoid the boundary spurs, a second time base reference is selected that can generate boundary spurs that do not overlap with the first time base. Circuitry is provided to select the appropriate time base and the fractional N values to generate desired output frequencies throughout the synthesizer range while avoiding the boundary spurs.

Abstract: Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.

Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (?p) differing by a power of two and situated in the vicinity of 2i?1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.

Abstract: A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Abstract: Provided is a waveform generating apparatus that generates a signal having an arbitrary waveform, comprising a waveform memory that stores a plurality of pieces of waveform data that each include a sequence of signal values; a filtering section that (i) reads from the waveform memory a piece of waveform data serving as a basis for a waveform to be generated, from among the plurality of pieces of waveform data, (ii) performs a conversion by filtering the read piece of waveform data to obtain a piece of converted waveform data, and (iii) writes to the waveform memory the piece of converted waveform data; and a waveform output section that reads the piece of converted waveform data from the waveform memory and outputs a signal having a waveform corresponding to the sequence of signal values of the read piece of converted waveform data.

Abstract: A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages.

Abstract: Disclosed are a sampling circuit and a receiver having a high flexibility of the filter design and excellent characteristics for removing an interfering wave. Provided also are a sampling circuit and a receiver having a low level of the higher harmonic spurious. The sampling circuit (100) includes: a charge sampling circuit (101) which executes sampling of an input signal; and a plurality of charge sharing circuits (102-1 to 102-N) connected in parallel to the output stage of the charge sampling circuit (101). The charge sharing circuits (102-1 to 102-N) includes: a charge sharing circuit group (102) having transmission functions different from one another; a synthesis circuit (103) which is arranged at the output side of the charge sharing circuit group (102) and synthesizes the outputs of the charge sharing circuits (102-1 to 102-N); and a digital control unit (104) which outputs a control signal for controlling the operation of the charge sharing circuit group (102) and the synthesis circuit (103).

Abstract: The provision of a technique capable of determining a state where PLL control does not operate normally instantly or in advance in a frequency synthesizer that frequency-divides, A/D converts, and quadranture-detects a frequency signal from a voltage controlled oscillating unit, and extracts a rotation vector rotating at a frequency difference between the frequency signal used for the detection and the A/D converted frequency signal, and integrates a difference between a frequency of the above rotation vector and a set frequency to set an integration result as a control voltage to the voltage controlled oscillating unit. The control voltage to be input to the voltage controlled oscillating unit is monitored, and it is determined whether or not a level of the monitored control voltage deviates from a set range determined in advance, and an unlock detection signal is output.

Abstract: A technique wherein when signals, the modulation schemes of which are different, are to be combined, performing the peak suppression using amounts of the respective modulation schemes can effectively reduce the PAPR of a resulting combined signal. A peak suppressing method for use in a peak suppressing circuit, which combines input signals of different modulation schemes in a time domain to provide a combined signal, comprises detecting, as a peak, that portion of the combined signal which excesses a threshold value to generate a peak signal in accordance with the peak; converting the peak signal into a frequency domain signal and then dividing it into signals originating from the input signals to use these input-signal-originated signals as respective suppression signals; and adding, to the input signals, the suppression signals having different suppression amounts for the respective modulation schemes, thereby performing the peak suppression.

Abstract: The universal CMOS current-mode analog function synthesizer is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks built around a basic current squarer, and a constant current. The circuit can simultaneously realize thirty-two different mathematical functions and can be easily expanded to accommodate many others.

Abstract: The present invention is directed to an integrated circuit device that includes a primary signal synthesizer configured to generate a free-running first digital frequency signal and at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer and configured to generate a free-running at least one second digital frequency signal. A switch element includes a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer. The switch element is configured to select a switch output that provides either the free-running first digital frequency signal or the free-running at least one second digital frequency signal based on a switch control input.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Abstract: Disclosed is a recursive, direct digital synthesizer includes an accumulator module and a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module. The CORDIC module rotates a signal according to a desired rotation angle specified by the accumulator module. An automatic gain control module is coupled to the CORDIC module. The automatic gain control module can apply a level of gain to the rotated signal.

Abstract: A phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from ?180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal.

Abstract: The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

Abstract: The universal CMOS current-mode analog function synthesizer is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks built around a basic current squarer, and a constant current. The circuit can simultaneously realize thirty-two different mathematical functions and can be easily expanded to accommodate many others.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: A triangular waveform generator is converted to a free running oscillator controlled by a calibration code. The free running oscillator can be synchronized to an external clock signal by comparing the external clock frequency to the frequency of the triangular waveform and adjusting the calibration code until the discrepancy in frequency is minimized.

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.