Having Digital Device (e.g., Logic Gate, Flip-flop, Etc.) Patents (Class 327/107)
  • Patent number: 11146280
    Abstract: A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 12, 2021
    Assignee: Tektronix, Inc.
    Inventors: Gregory A. Martin, Patrick Satarzadeh, John J. Pickerd, Daniel G. Knierim
  • Patent number: 10972084
    Abstract: A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 6, 2021
    Assignee: Microchip Technology Inc.
    Inventor: Michael R. Williamson
  • Patent number: 10972109
    Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Somnath Kundu, Stefano Pellerano, Abhishek Agrawal
  • Patent number: 10886934
    Abstract: A time to digital converter includes a state transition section configured to start, based on a trigger signal, state transition in which an internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with a reference signal, state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information, a time digital value corresponding to the number of times of transition of the internal state. The state transition section includes a tapped delay line to which a plurality of delay elements are coupled, a logic circuit, and a state machine. The state information is represented by count information output from the state machine and propagation information output from the tapped delay line. A hamming distance of the state information before and after the state transition is 1.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 5, 2021
    Inventor: Masayoshi Todorokihara
  • Patent number: 10782346
    Abstract: In described examples, a latch includes active feedback circuitry for latching input information. A comparison of logic states between input and output states at selected times can determine whether, for example, the latch has correctly retained latch data. The latch can optionally be included within a scan chain, provide asynchronous latch error notifications, and/or synchronous notifications indicating where in the scan chain a latch error occurred.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jose Flores, Rama Venkatasubramanian
  • Patent number: 10720930
    Abstract: A communication technique for converging internet of everything (IoT) technology with a 5th generation (5G) communication system for supporting a higher data transfer rate beyond a 4G system is provided. The communication technique can be applied to intelligent services, based on 5G communication technology and IoT-related technology. In an embodiment, an electronic device includes a first processor configured to output a first signal for generating a first frequency signal, a second processor configured to output a second signal for generating a second frequency signal, a first radio frequency (RF) chip configured to output the first frequency signal, based on the first signal received from the first processor and a baseband signal, and a second RF chip configured to output the second frequency signal, based on the second signal received from the second processor and the first frequency signal outputted from the first RF chip.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngchang Yoon, Kyuhwan An, Daehyun Kang, Juho Son, Sunggi Yang, Donghyun Lee, Yunsung Cho
  • Patent number: 10530252
    Abstract: A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 7, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Katsuyuki Imamura, Takeaki Moto
  • Patent number: 10520546
    Abstract: An automatic power supply system is electrically coupled to a component to be tested. The automatic power supply system includes a power array and a controller. The power array includes a plurality of power channels, and provides power supplies through the plurality of power channels. The component to be tested is electrically coupled to a first power channel of the plurality of power channels and receives a power supply through the first power channel. The controller is electrically coupled to the power array, and calculates a power of the power supply received by the component to be tested. The controller adjusts a power specification of the power supply provided through the first power channel according to the power.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 31, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Yu-Lin Chang, Kai-Yang Tung, Mao-Ching Lin
  • Patent number: 10511314
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10483982
    Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Hui Li, Teck-Chuan Ng, Stephen E. Aycock
  • Patent number: 10466289
    Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 5, 2019
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
  • Patent number: 10429882
    Abstract: A clock generator outputs a processor clock that serves as an operation reference for a processor for use in a content protection system. The clock generator includes a direct digital synthesis and a random number generator. The direct digital synthesizer includes a phase accumulator and outputs the processor clock. The phase accumulator accumulates a setup value in synchronization with a reference clock. The random number generator generates random numbers. The setup value changes based on the random numbers.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 1, 2019
    Assignee: MEGACHIPS TECHNOLOGY AMERICA CORPORATION
    Inventors: Alan Kobayashi, Sujan Thomas, Ramesh Dandapani, Johnny Garrett
  • Patent number: 10404263
    Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Vincent Onde, Jean-Francois Link
  • Patent number: 10389338
    Abstract: A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 20, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideyuki Nakamizo, Morishige Hieda, Hiroyuki Mizutani, Kenichi Tajima
  • Patent number: 10312064
    Abstract: A power supply system includes a digital-to-analogue converter (DAC) configured to generate an analogue signal and an amplifier path on which the analogue signal is amplified to generate a high-frequency power signal to be provided to a plasma chamber for supplying a plasma process with high-frequency power. The DAC is configured to be connected to an arc detection device that is configured to monitor the plasma chamber for arcs and be controlled by the arc detection device to modify the analogue signal in response to detecting an occurrence of an arc.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 4, 2019
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Daniel Krausse, Anton Labanc, Christan Thome, Alberto Pena Vidal
  • Patent number: 10263625
    Abstract: A TDC circuit includes a plurality of delay elements connected in series. The TDC circuit includes a reference signal supply circuit that randomly selects one of the plurality of delay elements to supply a reference signal. The TDC circuit includes a plurality of latch circuits that latch a clock signal in response to outputs of the plurality of delay elements. The TDC circuit includes an output circuit that codes output signals output from the plurality of latch circuits and outputs a digital code indicating a relative time relationship of the clock signal with respect to the reference signal.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 16, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takashi Tokairin
  • Patent number: 10241537
    Abstract: An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 26, 2019
    Assignee: Apple Inc.
    Inventors: Huaimin Li, Fabien S Faure, Shy Hamami, Pradeep Trivedi, Yaron Cohen
  • Patent number: 10153777
    Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 11, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reza Hoshyar, Wenting Zhou, Ali Kiaei, Baher Haroun, Ahmad Bahai
  • Patent number: 10122407
    Abstract: A system for radio scanning and signal generation including a direct digital synthesis (DDS) signal generator providing a signal within a first bandwidth; a frequency multiplier in signal communication with the DDS signal generator; the frequency multiplier adapted to convert the signal within the first bandwidth to a multiplied signal within a second bandwidth, wherein the second bandwidth encompasses a wider frequency range than the first bandwidth; a processor in communication with the DDS signal generator for programming the DDS signal generator to provide the signal within the first bandwidth; the processor further adapted to reprogram the DDS signal generator to alter the first bandwidth; a radio frequency (RF) port for transmitting the signal as a wideband signal.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: November 6, 2018
    Assignee: Allen-Vanguard Corporation
    Inventors: Trevor Noel Yensen, Travis Patrick Corkery
  • Patent number: 10049708
    Abstract: A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 14, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 10027333
    Abstract: An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 17, 2018
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Abhirup Lahiri, Nitin Gupta, Gagan Midha
  • Patent number: 10002749
    Abstract: An arc extinguishing method for extinguishing arcs in a plasma chamber of a plasma system, comprising providing a plasma operating power during a plasma operation to the plasma chamber for generating plasma in the plasma chamber and carrying out a plasma-processing process using the generated plasma, by generating an analog signal by a digital-to-analog converter (DAC) and amplifying the generated analog signal on an amplifier path, monitoring, by an arc detection device, the plasma system for arcs, and in response to detecting an occurrence of an arc, controlling the DAC by the arc detection device such that the generated analog signal by the DAC is modified.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: June 19, 2018
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Daniel Krausse, Anton Labanc, Christan Thome, Alberto Pena Vidal
  • Patent number: 9991006
    Abstract: A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 5, 2018
    Assignee: National University Corporation Nara Institute Of Science and Technology
    Inventors: Satoshi Ohtake, Hiroshi Iwata, Michiko Inoue
  • Patent number: 9954537
    Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 24, 2018
    Assignee: Seagate Technology LLC
    Inventors: Marcus Marrow, Kenneth John Evans, Jason Vincent Bellorado
  • Patent number: 9853646
    Abstract: A system and method for system, method and apparatus for phase hits and microphonics cancellation. In addition to a first RF synthesizer source, a device also includes a second stable reference signal source that operates at a lower frequency as compared to the RF synthesizer source. The second stable reference signal source is selected with good phase noise characteristics and can be used to correct phase error events.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: December 26, 2017
    Assignee: Maxlinear Asia Singapore PTE LTD
    Inventors: Igal Yehuda Kushnir, Ido Mordechai Bettesh, Yaacov Sturkovich
  • Patent number: 9813048
    Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: November 7, 2017
    Assignee: Purdue Research Foundation
    Inventors: Kaushik Roy, Mrigank Sharad
  • Patent number: 9787296
    Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Eun Lee, Kyung-Hoon Kim, Myeong-Jae Park, Woo-Yeol Shin, Han-Kyu Chi, Yong-Ju Kim
  • Patent number: 9740175
    Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 22, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Olivier Burg, Haisong Wang, Xiang Gao
  • Patent number: 9722832
    Abstract: A frequency control circuit, adapted to be utilized in a phase locked loop circuit. The frequency control circuit includes a first frequency control block, a second frequency control block, a pump control unit and a charge pump unit. The first frequency control block generates a first control signal according to a frequency of an output signal from the phase locked loop circuit, in which the first control signal is configured to control the frequency of the output signal located within a predetermined frequency region. The second frequency control block generates a second control signal according to a frequency of an input signal and the frequency of the output signal, in which the second control signal is configured to control the frequency of the output signal located at a target frequency.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 1, 2017
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shih-Che Hung, Chun-Liang Chen
  • Patent number: 9705613
    Abstract: This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 11, 2017
    Assignee: Intel IP Corporation
    Inventors: Ashoke Ravi, Ofir Degani, Hasnain Lakdawala
  • Patent number: 9571927
    Abstract: This application relates to digital-to-analogue conversion with improved noise performance. Embodiments relate to digital-to-analogue conversion circuits (300) for converting a digital audio signal to an analogue audio signal having a digital-to-analogue converter (104) operable at a plurality of DAC clock rates. A first clock controller (301-1) controls the DAC clock rate based on an indication of the amplitude of the audio signal. The DAC clock rate (CK1) may be increased for low amplitude signal, where noise is important, to reduce the in-band thermal noise of the DAC. At higher amplitudes, when noise is less audible, the DAC clock rate may be reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector (302) or in some cases by an analogue level detector (303).
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: February 14, 2017
    Assignee: Cirrus Logic International Semiconductor Ltd.
    Inventor: John Paul Lesso
  • Patent number: 9491389
    Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 8, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
  • Patent number: 9490828
    Abstract: A phase-locked loop (PLL) integrated circuit includes multiple digitally-controlled oscillators (DCOs), which are slaved to the same feedback loop filter. This PLL includes a frequency control circuit, which is configured to generate a control signal and is responsive to a first periodic reference signal (e.g., REFCLK). The plurality of DCOs include a corresponding plurality of independently-programmable fractional dividers, which are configured to generate a respective plurality of periodic PLL output signals of different frequency in response to a second periodic reference signal (e.g., SYSCLK). The plurality of DCOs include corresponding scaling circuits, which are each responsive to the control signal. The plurality of scaling circuits are configured to scale the control signal to different degrees to thereby make effective gains of the DCOs more nearly equal.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 8, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Song Gao
  • Patent number: 9455666
    Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Ming-Chieh Huang, Tien-Chun Yang
  • Patent number: 9429919
    Abstract: A delay line operates to propagate a plurality of delay stages comprising a first delay element and a second delay element. A generator coupled to the delay line is configured to provide the start edge to the plurality of delay stages of the delay line as a function of a digital control oscillator (DCO) counter value generated by a DCO counter. A DCO calculation component is configured to facilitate a determination of propagation counts of the delay line as a function of DCO periods of a DCO.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 30, 2016
    Assignee: Intel Deutschland GmbH
    Inventor: Markus Schimper
  • Patent number: 9432027
    Abstract: A frequency control system includes a power generating circuit and a frequency generating circuit. The power generating circuit includes an up transistor circuit, a down transistor circuit and a capacitor for generating a stable voltage. The frequency generating circuit includes a digital-to-analog converter (DAC), a current source/sink circuit, a voltage-controlled oscillator (VCO) and a digital controller. The DAC receives the stable voltage as a power, the current source/sink circuit receives an analog signal from the DAC, the VCO receives a control voltage from the current source/sink circuit, and the digital controller receives a frequency signal from the VCO and a reference signal, according to which a digital signal is generated and fed to the DAC.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: August 30, 2016
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Patent number: 9423441
    Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: August 23, 2016
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
  • Patent number: 9397667
    Abstract: A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventor: Árni Ingimundarson
  • Patent number: 9344268
    Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 17, 2016
    Assignee: Broadcom Corporation
    Inventors: Ali Nazemi, Burak Catli, Wayne Wah-Yuen Wong, Kangmin Hu, Hyo Gyuem Rhew, Delong Cui, Jun Cao, Bo Zhang, Afshin Doctor Momtaz
  • Patent number: 9262233
    Abstract: A method and/or computer for a tuned spin count in a multithreaded system determines a re-calculation time interval at which to re-calculate a current spin lock value. Then, a spin-lock-re-calculation is repeatedly executed at the re-calculation time interval to perform: observing a current environment of the multithreaded system, determining, using a second-order tuning and values of the current environment, a dynamically calculated heuristic to provide the newly-recalculated spin lock value, and memorizing the newly re-calculated spin lock value, in a memory, as the current spin lock value. Meanwhile, thread(s) in the multithreaded system which want to execute a spinlock will obtain the current spin lock value which is memorized in the memory, and execute the spin lock using the current spin lock value to set a length of the spin lock.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: February 16, 2016
    Assignee: Software AG
    Inventors: Christopher Reed, Mark Horsburgh, Matthew Johnson
  • Patent number: 9172359
    Abstract: A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block generates phase values in increments of the fine time step, each phase value also offset from other phase values by multiples of a coarse time step. The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 27, 2015
    Assignee: RAYTHEON COMPANY
    Inventor: Howard S. Nussbaum
  • Patent number: 9160347
    Abstract: A method and apparatus for operating an electronic device is provided. The electronic device, which includes a phase lock loop (PLL) receives sensor indicators from at least one sensor. Upon receiving sensor indicators, the device identifies a motion indicator based on the sensor indicators. A parameter of the PLL is adjusted based on the motion indicator, the PLL having at least one component susceptible to microphonics. When the PLL includes a charge pump, a parameter that may be adjusted is a pump current of the charge pump. When the PLL further comprises an oscillator for generating a reference signal, the parameter that may be adjusted is a trim of the oscillator.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Symbol Technologies, LLC
    Inventors: Irfan Kadri, Chu Pang Alex Ng
  • Patent number: 9118275
    Abstract: An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 25, 2015
    Inventor: Liming Xiu
  • Patent number: 9071195
    Abstract: The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: June 30, 2015
    Assignee: SAVANT TECHNOLOGIES LTD.
    Inventor: David Gabbay
  • Patent number: 9065478
    Abstract: A digital-to-analog conversion apparatus to convert a digital signal to an output analog voltage signal includes an analog-to-digital conversion processing circuit and an analog voltage signal output circuit. The analog-to-digital conversion processing circuit is configured to increase a resolution of the digital-to-analog conversion apparatus without increasing a frequency of an input clock signal. The analog voltage signal output circuit is configured to generate the output analog voltage signal based on the input clock signal at the increased resolution of the digital-to-analog conversion apparatus.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-kook Kim, Sang-yong Park, Chan-woo Park, Young hoon Lee, Byeong-ha Park
  • Publication number: 20150123713
    Abstract: A digital/analog converter (30) with a first return-to-zero unit (311) which is connected to a first busbar (321), wherein the first busbar (321) is connected in each case to a first output of several differential units (351, 352, 35n). In this context, the first return-to-zero unit (311) provides at least one clock input which is directly or indirectly connected to a first photodiode, wherein the first photodiode is fed from a pulsed light source (5).
    Type: Application
    Filed: April 24, 2013
    Publication date: May 7, 2015
    Inventor: Gerhard Kahmen
  • Patent number: 9000618
    Abstract: A transmission line driver and a method for driving the same are provided, in which a composite current source is provided as an input current source, such that an output voltage is fixed. The composite current source includes an internal current source and an external current source. The composite current source is supplied to a single-ended transmission line driver or a differential transmission line driver, such that the output voltage is fixed.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: April 7, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Su-liang Liao
  • Patent number: 8982657
    Abstract: A semiconductor device includes: a plurality of target lines to be driven; a plurality of target line drivers configured to drive the corresponding target lines in a logic level corresponding to a plurality of target line selection signals; a plurality of booster enable units configured to generate a booster enable signal by sensing whether a group of target lines that is obtained by grouping the target lines by a predetermined number is enabled or not; and a plurality of self-boosters configured to boost corresponding target lines by sensing levels of the corresponding target lines in response to the booster enable signal.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jeongsu Jung
  • Patent number: 8975952
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Patent number: 8963750
    Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: David Canard, Julien Delorme