Abstract: A dividing apparatus is provided. The dividing apparatus includes a frequency dividing circuit and a noise reducing circuit. The frequency dividing circuit is arranged to receive a first clock signal and generate a frequency divided signal corresponding to the first clock signal. The noise reducing circuit is coupled to the frequency dividing circuit and arranged to receive a second clock signal and the frequency divided signal, and is utilized for referring to the second clock signal and the frequency divided signal to reduce noise of the frequency divided signal to generate a noise-reduced frequency divided signal. The first and second clock signals may be identical clock signals or different clock signals.

Abstract: Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages.

Abstract: Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.

Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.

Abstract: A clock dividing circuit includes a control logic unit and a flip-flop. The control logic unit outputs an enable signal and a data signal according to a clock signal and a division ratio. The flip-flop outputs a divided clock signal based on the clock signal, the enable signal and the data signal. The clock signal can be directly outputted as the divided clock signal through the flip-flop.

Abstract: A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.

Abstract: Example embodiments are directed toward configuration of a phase lock loop (PLL) circuits for low power operation. In particular embodiments, a fraction related to a desired gain of a PLL circuit is determined. A set of possible frequency-divider values and a set of possible feedback divider values are determined. A PLL configuration is selected from a combination of the sets of frequency divider and feedback divider values that forms a ratio indicated the determined fraction.

Abstract: A time to digital converter includes: a delay circuit having a plurality of delay stages that delay an input clock signal in multiple stages, at least one of the delay stages being a variable delay stage; a plurality of flip flops that capture outputs of the delay stages corresponding thereto in a one-to-one relation in response to input of a reference signal; an edge detecting circuit that detects changing edges of respective outputs of the flip flops; a counter circuit that counts a number of edges detected by the edge detecting circuit; and a control circuit that controls a delay amount of the variable delay stage according to the number of edges counted by the counter circuit.

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors, The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract: A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.

Abstract: A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be programmable by writing the N-bit value to a register. The divisor may be even or odd. During operation, the clock divider may decrement a counter down from an initial value (derived from the N-bit value representing the divisor) to a trigger value. When the trigger value is detected, the clock divider may cause the output clock to toggle. The trigger value may depend on whether the divisor is even or odd. The clock divider may be re-programmed during operation by writing a new N-bit value into the register. Re-programming may include changing the divisor from an even value to an odd value.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.

Abstract: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

Abstract: Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

Abstract: A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

Abstract: A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts.

Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.

Abstract: A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.

Abstract: A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register within the preset register group, and imparts the dividing ratios stored in the selected preset register to the plurality of dividers.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: Frequency divider circuits and architectures, and methods of implementing and using the same, are disclosed. In one embodiment, the frequency divider circuit includes a dynamic section that receives an input signal and outputs an intermediate signal that has a frequency lower than that of the input signal; and a static section that receives the intermediate signal and outputs a signal having a frequency that is lower than that of the intermediate signal. Stages in the dynamic and/or static section can be implemented using thin film transistors (TFTs). Embodiments of the present invention advantageously provide an approach that takes overcomes problems associated with the leakage and speed characteristics of TFTs.

Abstract: To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Abstract: A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operative to generate a second frequency divided signal. A third frequency divider stage is coupled to the clock signal and to the second frequency divider stage and is configured to generate a third frequency divided signal using only i) the clock signal and ii) the second frequency divided signal so that any transition of the third frequency divided signal occurs at an edge of the clock signal at which the second frequency divided signal does not transition.

Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle.

Abstract: A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be programmable by writing the N-bit value to a register. The divisor may be even or odd. During operation, the clock divider may decrement a counter down from an initial value (derived from the N-bit value representing the divisor) to a trigger value. When the trigger value is detected, the clock divider may cause the output clock to toggle. The trigger value may depend on whether the divisor is even or odd. The clock divider may be re-programmed during operation by writing a new N-bit value into the register. Re-programming may include changing the divisor from an even value to an odd value.

Abstract: A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair.

Abstract: A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.

Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.

Abstract: A frequency synthesizer is provided, including a voltage-controlled oscillator (VCO), a frequency prescaler, a divide-by-2.5 circuit, and a selector. The VCO determine the frequency of a first signal according to an input voltage. The frequency prescaler determines the frequency of a second signal to be the frequency of the first signal divided by 3, 3.5, or 4 according to a first selection signal, and the frequency prescaler also determines the frequency of a third signal to be the frequency of the first signal divided by 6, 7, or 8 according to the first selection signal. The divide-by-2.5 circuit generates a fourth signal, wherein the frequency of the fourth signal is the frequency of the first signal divided by 2.5. The selector selects one of the second signal, the third signal, and the fourth signal as a fifth signal according to a second selection signal.

Abstract: In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

Abstract: A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; and (b) a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal.

Abstract: A band converted signal generator includes a low range characteristic application section (16) as a component emphasis means emphasizing only one or more specific frequency components selected from among frequency components of an input signal; and a low pass filter (17) as a component extraction means extracting a signal component of a desired frequency band from an output signal supplied from the low range characteristic application section (16). A band extender (1000) includes the above-mentioned band converted signal generator, and an adder (15) adding the input signal, a certain frequency band of which is suppressed, and a signal including at least one component generated within the certain frequency band which is suppressed.

Abstract: A clock frequency divider circuit 11 according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by masking (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency divider circuit 11 includes a mask control circuit that generates a mask signal in which a non-mask timing is preferentially assigned to a clock pulse at a timing at which no clock pulse exists in a clock signal used in a circuit Ai other than a target circuit Bi using the output clock signal among S clock pulses of the input clock signal, and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.

Abstract: A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

Abstract: A mask circuit (10) masks the clock pulses of a clock S in accordance with an input mask signal (50), generating and outputting a clock B. A mask control circuit (20) generates a mask signal (50) which assigns mask timings to mask (M?N) clock pulses, to timings other than communication timings to perform data communication, out of the timings of M successive clock pulses of the clock S, based on communication timing information (30) indicating the communication timings of data communication that is performed with a circuit A by a circuit B using the clock B. The mask control circuit (20) then outputs the mask signal (50) to the mask circuit (10).

Abstract: Embodiments of apparatuses, articles, methods, and systems for a synthesizer with an extended multi-modulus prescaler are generally described herein. Described embodiments include an offset controller that provides an offset to a first counter value and a multi-modulus prescaler to implement a first modulated division number based on the first counter value and a second counter value. The offset controller may compensate for the offset to provide a second modulated division number based on the first modulated division number. Other embodiments may be described and claimed.

Abstract: In order to help convert serial data, which includes extra protocol encoding bits, to parallel data having the protocol bits removed (or at least separated from the actual data), the serial data is at least partially deserialized using a low-speed clock having different frequencies at different times (typically different fractions of a high-speed serial data clock frequency at different times). This enables the partially deserialized data to include blocks of different numbers of the serial data bits. These blocks can be further assembled into groups of blocks having numbers of bits that correlate well with the number of bits in incoming serial data words. These groups can then be easily manipulated (e.g., to identify in them their extra protocol encoding bits). The circuitry can be set up to work with any of several different protocol encoding scheme.

Abstract: A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.

Abstract: A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.

Abstract: A programmable frequency divider, which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies, includes a divided clock generator dividing a frequency of an input clock signal Fin by a first divide ratio (N+1) or a second divide ratio N according to a divide ratio control signal MC to generate a plurality of divided clock signals Dout; a counting unit counting the number CNT of the plurality of divided clock signals Dout, by performing swallow mode counting and program mode counting sequentially on the plurality of divided clock signal Dout; a control signal generator generating the divide ratio control signal MC, using the number CNT of the plurality of divided clock signal Dout, a count S by the swallow mode counting and a count P by the program mode counting, the count P corresponding to a maximum of the number CNT, feeding the divide ratio control signal MC back to the divided clock generator, and generating a reset control signal RST for resettin

Abstract: A master stage 101 comprises a differential circuit composed of transistors 1 and 2, a differential circuit composed of transistors 3 and 4, a differential circuit composed of transistors 5 and 6, a load circuit 7 (a first load circuit), a load circuit 8 (a second load circuit), and a current source transistor 9. The load circuit 7 (the first load circuit) is composed of an inductor 7A (a first inductor), an inductor 7B (a fifth inductor), and a capacity 7C (a first capacity). The inductor 7B and capacity 7C cooperates together in forming a parallel resonance circuit (a first LC parallel resonance circuit), while the parallel resonance circuit is connected in series to the inductor 7A.

Abstract: Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

Abstract: A divider is disclosed that presents an enhanced duty cycle for use with precision oscillators in clock sources. In one example, the invention includes a first divider chain to receive an input clock and produce a first divided output, a second divider chain to receive the input clock and produce a second divided output, and a combiner to combine the first and second divided output to produce a third divided output with a duty cycle greater than the first and second divided output.