Abstract: A semiconductor device includes a power supply; and a plurality of processor cores configured to operate with the power supply, wherein each of the plurality of processor cores includes a clock control circuit that decreases an own clock frequency used by an own processor core when detecting drop of a power supply voltage of the own processor core, and adjusts a speed at which the own clock frequency is increased according to a situation of a power supply voltage of another processor core among the plurality of processor cores.

Abstract: An input/output apparatus for a PLC includes at least first and second sub-systems. In each sub-system, a DC-DC converter controls a voltage of an external power supply to a target voltage by switching a PWM signal, and a microcomputer is driven by a clock signal. In the microcomputer, a PWM signal generating unit generates the PWM signal and a frequency analyzing unit samples an inputted voltage at a cycle shorter than a cycle of the PWM signal, and analyzes the frequency of the inputted voltage. The frequency analyzing unit acquires a frequency of the PWM signal from the frequency of the inputted voltage, calculates a frequency of the clock signal, and outputs an abnormality-notifying signal when the frequency of the clock signal falls outside a prescribed range. An output voltage of the DC-DC converter of the first sub-system is inputted to the frequency analyzing unit of the second sub-system.

Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.

Abstract: Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Abstract: A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.

Abstract: A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.

Abstract: A signal converter circuit includes a frequency detection circuit configured to determine whether an external control signal is a PWM signal. A PWM frequency converter circuit is configured to detect, when a PWM signal is input, a duty cycle of the PWM signal and to generate a first digital signal. An AD converter is configured to generate a second digital signal based on an input DC voltage or a voltage attributable to a variable resistor to digital data using a maximum AD convertible input voltage as a duty cycle of 100%. An output signal generation circuit is configured to generate, based on the first or second digital signals output from the PWM frequency converter circuit or the AD converter, a PWM signal with a duty cycle based on that first or second digital signals.

Abstract: A downhole tool for operation within a wellbore and including a transmitter array and first and second receiver arrays. The transmitter array includes a plurality of transmitters azimuthally distributed around a longitudinal axis of the downhole tool at a first axial location of the downhole tool. The first receiver array includes a plurality of first receivers azimuthally distributed around the longitudinal axis at a second axial location axially offset from the first axial location. The second receiver array includes a plurality of second receivers azimuthally distributed around the longitudinal axis at a third axial location axially offset from the first and second axial locations.

Abstract: In an I/O module, a communication enables communications between first and second external devices upon a voltage being supplied from a power source thereto. A shutoff switch shuts off supply of the voltage to the communication controller when turned off. A capacitor is charged based on the voltage supplied from the voltage source while the shutoff switch is in an on state. The capacitor supplies an operating voltage to the communication controller while the shutoff switch is turned off. The communication controller detects a voltage across the capacitor as a diagnostic voltage, and outputs a turn-off command to the shutoff switch for turning off the shutoff switch. The communication controller determines whether there is a fixedly closed malfunction in the shutoff switch based on the diagnostic voltage while outputting the turn-off command to the shutoff switch.

Abstract: A controlling method for optimizing a processor is provided. The controlling method includes determining an actual utilization state of the processor in a first period, and adjusting performance and/or power of the processor in a second period by a PID (Proportional Integral Derivative) governor based on the actual utilization state in the first period. The second period is after the first period.

Abstract: A bandgap reference (BGREF) circuit includes at least one switch capacitor impedance element including a capacitor coupled with switches that receive a reference frequency. The at least one switch capacitor element is coupled with at least one diode. The BGREF circuit is operative to create a voltage reference.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.

Abstract: A vehicle includes a traction battery, an electric machine, and a variable voltage converter. The variable voltage converter includes an inductor and is disposed electrically between the traction battery and electric machine. The vehicle also includes a controller programmed to issue duty cycle commands for the variable voltage converter based on a product of an AC component of current flowing through the inductor and a calibrated resistance.

Abstract: An adaptive Vcom level generator circuit generates a variable Vcom voltage level. A variable Vcom voltage can be used for variable refresh rate display technology to prevent flicker on a display panel. The Vcom level can be changed based on the vertical frequency being used or can be changed based on external control signals.

Abstract: Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.

Abstract: A data synchronizer that registers an input data signal into a clock domain of a clock signal. The data synchronizer includes in input circuit, first and second pass gates, first and second inverters, gate controller, and a register. The input circuit drives first and second data nodes to opposite logic states based on the input data signal. Each pass gate is coupled between a data node and a capture node. The inverters are cross-coupled between the capture nodes. The gate controller is capable of keeping the pass gates at least partially open during a metastable condition of the capture nodes, and closes the pass gates when the capture nodes resolve to opposite logic states. The register registers a capture node to provide a registered data output in response to the clock signal. The data synchronizer may be implemented using FinFET devices.

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Abstract: A phase-locked loop circuit, which includes a phase frequency detector, a charge pump, a loop low-pass filter, a first voltage-current converter, a second voltage-current converter, a current-controlled oscillator, a frequency divider, a comparator, and a mode controller, where the mode controller is configured to control the switches S1, S2, and S3 included in the loop low-pass filter to connect or disconnect. Using the phase-locked loop circuit, a voltage value of a second control voltage signal VC2 provided for the first voltage-current converter can reach, in a relatively short time, a voltage value of a first control voltage signal VC1 provided for the second voltage-current converter, thereby increasing a speed of establishing the phase-locked loop circuit and implementing a quick response of the phase-locked loop circuit.

Abstract: In one embodiment, individual or groups of heat generating data processing operations are rate-controlled such that a component, a set of components, a board or line card, and/or an entire apparatus or any portion thereof stays within a corresponding heat budget. One or more heat price tags are associated with these data processing operations which are used to determine whether or not a corresponding data processing operation can be currently performed within one or more corresponding heat budgets. If so, the data procession operation proceeds. If not, the data processing operation is delayed. Examples of such data processing operations include, but are not limited to, data retrieval from memory, data storage in memory, lookup operations in memory, lookup operations in a binary or ternary content-addressable memory, regular expression processing, cryptographic processing, or data manipulation.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing.

Abstract: A PWM signal generating circuit and method, and an LED driver circuit using same, is disclosed. The PWM signal generating circuit generates a PWM signal for a DC-DC converter using a dimming signal, and includes an oscillator which generates a first clock signal having a predetermined frequency, a synchronizing unit which synchronizes the dimming signal to the first clock signal, and a PWM signal generating unit which generates the PWM signal in response to the first clock signal having a falling edge while the synchronized dimming signal is on.

Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract: A driving circuit includes a first PWM driving module and a second PWM driving module. The first PWM driving module generates a first square-wave signal to drive a first illumination unit according to a first data signal of a data stream, wherein the first square-wave signal, having a rising edge located at the beginning of the display cycle, represents an illumination period of the first illumination unit in a display cycle. The second PWM driving module generates a second square-wave signal to drive a second illumination unit according to a second data signal of the data stream, wherein the second square-wave signal, having a falling edge located at the end of the display cycle and having a rising edge being behind the rising edge of the first square-wave signal, represents an illumination period of the second illumination unit in the display cycle.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.

Abstract: A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: An operation clock generation circuit performs calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal and an output terminal for outputting an output signal.

Abstract: Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit includes a multiplexer and a logic module coupled to the multiplexer. The multiplexer is configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. The logic module includes at least one of an XNOR and an XOR module and is configured to provide an output signal that is responsive to performing at least one of an XNOR and an XOR operation of the output of the multiplexer and an enable signal that enables or disables the clock gate circuit to generate the clock signal.

Abstract: A method and apparatus to drive a load using a pulse-width modulated (PWM) signal and spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a constant duty cycle for the load.

Abstract: Here, an apparatus is provided. The apparatus comprises a first supply rail, a second supply rail, a first ambipolar transistor (which is coupled to the first supply rail at its drain and which receives a reference voltage at its gate), a second ambipolar transistor (which is coupled to the first supply rail at its drain and which receives an input signal at its gate), a current source (which is coupled between the sources of the first and second ambipolar transistors and the second supply rail), and an output circuit (which is coupled to drain of the first ambipolar transistor). In operation, the output circuit provides an output signal having a frequency that is about twice the frequency of the input signal.

Abstract: A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.

Abstract: Groups of phase shifted PWM signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

Abstract: A method for calibrating frequency, applicable to calibrating a frequency signal generated by a frequency generating unit of an apparatus at a preset frequency, includes obtaining the cycle number of the clock rate of a frequency signal based on a reference signal and a clock mask synchronous with the frequency signal; obtaining a frequency of the frequency signal based on the cycle number; correcting the frequency according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the frequency signal by increasing the quantity of the phase shift signals, so as to calibrate the frequency signal generated by the frequency generating unit.

Abstract: A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit 803 including a grounded-gate MOS transistor M1 with a source into which an input signal is input, and a grounded-source MOS transistor M2 with a gate into which the input signal is input; a frequency converter 802 for converting frequencies of a first current signal output from the grounded-gate MOS transistor M1 and a second current signal output from the grounded-source MOS transistor M2, and for generating a third current signal and a fourth current signal; a load MOS transistor M7, with a gate and a drain connected, for receiving a third current signal; and a load MOS transistor M8, with a gate and a drain connected, for receiving a fourth current signal.

Abstract: The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal.