Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

Abstract: The clock divider circuit includes a dividing circuit, a selection circuit, and a synchronization circuit. The dividing circuit is configured to receive an input clock signal at a first frequency, and to produce a number of different periodic signals based thereon. The selection circuit is configured to receive various ones of the periodic signals. An output clock signal may be provided from the selection circuit based on a selection made therein. The input clock signal may have a frequency that is an integer multiple of the output clock frequency. The selection circuit is configured to provide the output clock signal at different, selectable frequencies. The synchronization circuit may control the timing of the switching of the output clock signal from one frequency to the next so that such switching may be performed without glitches.

Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Abstract: A transmission protocol decoding method, device, and a transport protocol decoder chip are provided for generating an oscillation signal; detecting a frame start signal, and outputting a sampling control signal when the frame start signal is detected; counting an oscillation period of the oscillation signal within a time period of low level bits of a frame start byte to obtain a count value after receiving the control signal, and then processing a division operation to the count value to output a quotient and a remainder; determining a sampling period according to the quotient and the remainder to generate a sampling pulse, and then decoding a data byte of a transmission data according to the sampling pulse.

Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.

Abstract: A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors. The first and fourth transistors are p-channel transistors. The second and fifth transistors are n-channel transistors. In the third and sixth transistors, an oxide semiconductor layer includes a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor. A low voltage is applied to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor.

Abstract: A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry.

Abstract: Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an output signal generally includes first and second flip-flops; first, second, and third logic circuits, each configured to function equivalently to a logic OR gate; and an internal frequency dividing circuit configured to generate an output waveform having a frequency that is one half that of an input waveform.

Abstract: One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

Abstract: Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.

Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.

Abstract: A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.

Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

Abstract: An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: The invention concerns a device for providing a spread frequency clock signal, comprising: —an input (51) to receive a first clock signal having a first frequency; —a programmable clock divider (52) to generate the spread frequency clock signal from the first clock signal; —a first Feedback Shift Register (21), FSR, comprising at least one stage, the FSR being adapted to generate any of an odd number M of different values, the FSR being adapted to pseudo-randomly generate a first sequence of first output values, each corresponding to one of said M different values, and to provide a first output value, according to the sequence, during each clock cycle of the spread frequency clock signal; —a control unit (22) adapted to select a division factor of the programmable clock divider based on the first output value of the FSR during each clock cycle of the spread frequency clock signal; —an output (53) for providing the spread frequency clock signal.

Abstract: Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.

Abstract: An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock.

Abstract: A fractional frequency divider circuit includes: a frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N; a clock addition circuit configured to add one clock to an output of the frequency divider circuit; a counter that counts the number of cycles of the output of the frequency divider circuit by a carry of the frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the frequency divider circuit as an output clock when the match is not detected.

Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal.

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

Abstract: Various embodiments relate to frequency dividers. A current of a current source of the frequency divider is controlled based on a property of an output signal of the frequency divider.

Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.

Abstract: A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

Abstract: An embodiment of a system for generating a low phase noise sine wave includes a variable signal source for generating a signal a series of octave dividing stages connected with the variable signal source, an input divider connected with the variable signal source, and a second series of octave dividing stages connected with an output of the pre-input frequency divider. Each octave dividing stage generating a successive octave of the generated signal using a frequency divider, a sine look up table, and a low pass filter.

Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

Abstract: Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a non-unity fraction of an input frequency of the input signal.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.

Abstract: A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.

Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.

Abstract: A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.

Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal.

Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.