Abstract: The jitter reduction circuit to reduce phase noise in a pulse train, comprises: —a resettable integrator (70) to integrate the pulse train, —a comparator (72) to compare the integrated pulse train with a reference level and to generate a modified pulse train with reduced phase noise, —a crossing time interval detector (94) configured to determine a discrete time interval during which the integrated pulse train crosses the reference level and to reset the integrator between two discrete time intervals determined consecutively.

Abstract: A ramp signal generator is provided. The ramp signal generator may include a ramp signal generation unit configured to generate a ramp signal based on an externally-supplied driving voltage and a ramp signal correction unit configured to feed back and compare the ramp signal with a reference signal and correct a driving voltage by generating a corrected voltage from a comparison value. The ramp signal generation unit may generate a corrected ramp signal where the slope changes based on a corrected driving voltage.

Abstract: A slope compensation method and circuit for a peak current control mode power converter circuit is provided. Since the power converter circuit has a synchronous signal of a driven signal of enabling the first primary switch and the second primary switch, a triangular wave signal is generated. The driven signals of the first and second primary switches determine the ramp up time of the triangular wave signal. The triangular wave signal is added to one of the output DC voltage feedback signal of the corresponding power converter circuit that are used to compare with a current peak value of the voltage feedback signals. Therefore, a high level triangular wave DC voltage feedback signal that is higher than the DC voltage feedback signal is formed, and the switching noises do not effect comparing result of a PWM controller of the power converter circuit.

Abstract: The transmitter comprises a signal generator including a capacitor producing the switched signal to be applied to the line. The capacitor is charged by a charging current in response to an input signal so as to define an edge of the switched signal through a feedback loop responsive to the capacitor voltage generating a feedback current having a continuous magnitude that is a progressive function of the capacitor voltage, the charging current being a function of the feedback current. The feedback loop generates first and second feedback voltages one of which is a rising function of the capacitor voltage and the other is a falling function of the capacitor voltage. The feedback current is generated first as a function of one of the feedback voltages and subsequently as a function of the other of the feedback voltages.

Abstract: A method and integrated circuit for the transmission of differential signals with a signal and a complementary signal is disclosed. For trimming the edge steepness of the signal with that of the complementary signal, the integrated circuit has a first driver for generating the signal, and a second driver for generating the complementary signal. A circuit is provided, configured to control the edge steepness of the signal or of the complementary signal.

Abstract: A sawtooth wave generating apparatus includes a base frequency generating section and a frequency generating section for generating the frequency of a reference signal, a sawtooth wave forming section which forms a sawtooth wave based on the reference signal, a voltage comparator which compares the voltage value of the sawtooth wave formed by the sawtooth wave forming section with a predetermined voltage value, a phase comparator which compares the phase of the output signal from the voltage comparator with the phase of the reference signal, and a low-pass filter (LPF) which cuts out a high frequency component of the output signal from the phase comparator, and feeds back the resulting output signal to the sawtooth wave forming section.

Abstract: Zero crossings for a non-symmetrical VIN may be determined by first amplifying and clipping VIN to create a non-symmetrical square wave whose zero crossings are those of VIN. A selected polarity edge of the non-symmetrical square wave may be taken as a 0° indicator and is used to create a fundamental sawtooth ramp of the same frequency and in phase with VIN. The fundamental sawtooth ramp starts at zero volts, linearly ramps to some peak and is AC coupled to a comparator whose other input is zero volts. That creates a square wave that is symmetrical as to its half-cycles, and whose every other edge is synchronous with the start of the fundamental sawtooth ramp, and whose intervening edges occur in the middle of the ramp. The intervening edge is detected and taken as a 180° indicator.

Abstract: A waveform generating circuit is provided which generates a modified triangular wave signal suitable for being input to a frequency modulation circuit such as a voltage-controlled oscillator (VCO). The waveform generating circuit includes a triangular generator, an offset generator for generating first and second offset component signals, a combiner for adding the triangular wave signal generated by the triangular wave generator and the offset component signals, and an output for delivering an output signal resulting from the addition by the combiner.

Abstract: A switching regulator that includes a switching transistor configured to control an output current by switching, a proportional current generator configured to generate a current proportional to a current flowing through the switching transistor, a first slope voltage generator configured to generate a linear slope voltage, a second slope voltage generator configured to generate a slope voltage having a secondary curve characteristic by integrating the current proportional to the current flowing through the switching transistor, and a slope voltage compensation circuit to generate a superimposed slope voltage formed by superimposing an output voltage of the first slope voltage generator on an output voltage of the second slope voltage generator.

Abstract: A sawtooth wave generating apparatus includes a base frequency generating section and a frequency generating section for generating the frequency of a reference signal, a sawtooth wave forming section which forms a sawtooth wave based on the reference signal, a voltage comparator which compares the voltage value of the sawtooth wave formed by the sawtooth wave forming section with a predetermined voltage value, a phase comparator which compares the phase of the output signal from the voltage comparator with the phase of the reference signal, and a low-pass filter (LPF) which cuts out a high frequency component of the output signal from the phase comparator, and feeds back the resulting output signal to the sawtooth wave forming section.

Abstract: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is acquired and compared with the triangular-wave signal at a comparator to generate a square-wave having a duty cycle of 50%. Then, the square-wave signal is used for triggering at positive and negative edges to generate a double frequency signal. As such, the high cost issue and the limitation of a square-wave input signal occurred in the prior art may be efficiently overcome.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: Generating a waveform having one signal level periodically and different signal levels in other durations. Two input signals are received, one having a desired constant level and another having desired signal levels. The desired output waveform is generated by selecting one of the two input signals. As a result, the output waveform may be generated to have (transitions) with high frequency even if the signal levels between adjacent portions are substantially different. Such waveforms are useful to test CDS (correlated double sampling) samplers.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: A ramp capacitor CAP1 has a first terminal connected to a power supply voltage VBAT. A generator circuit is connected to a second terminal of the ramp capacitor and adapted to generate a voltage ramp at the terminals of the ramp capacitor. The generator circuit includes a constant current source SCC connected to the second terminal B12 of the ramp capacitor CAP1 and auxiliary circuit MAX adapted in the presence of a transient variation of the power supply voltage to determine the transient current flowing in the ramp capacitor and generated by the transient variation. Responsive thereto, delivery is made to the second terminal B12 of the ramp capacitor CAP1 of a charging current equal to the algebraic sum of the constant current delivered by the constant current source and an auxiliary current equal and opposite to the transient current.

Abstract: A fast scanning voltage ramp generator including at least one chain of N two-pole avalanche transistors in series and a set of N+1 zener diodes in series between a high voltage power supply and ground, where N is an integer number≧2. A streak camera can utilize this type of generator.

Abstract: The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement (10) is provided with a device (20) for detecting the time history of an output voltage that is output and supplied to a load (12) by means of the driver/s (90). The measured time values are converted into an output voltage value in a device (36) for converting the measured time history of the output voltage. Moreover, a device (40) for generating a reference voltage value is provided. The device (40) is connected to a device (60) for predetermining a desired slope time for the driver/s (90), whereby the slope time is essentially independent of external conditions.

Abstract: Circuitry for ramping a voltage across a load 506 includes a charging circuit 500 for charging a capacitor 501 to generate a ramp-up wave form. Circuitry 511 selectively decouples a first driver 510 from load 506 during a ramping up mode and couples first driver 510 to load 506 during a normal operating mode. Ramp up driver 507a is selectively coupled to the load 506 during the ramp-up mode for ramping up the voltage across load 506 in response to the ramp-up wave form generated by charging circuitry 500. A discharge circuit 503d, 514a,b discharges capacitor 501 to generate a power-down wave form. Circuitry 511 selectively decouples a first driver 501 from output load 506 during the ramping down of the voltage across output load 506. A ramp-down driver 507b selectively ramps-down the voltage across output load 506 in response to the ramp-down wave form generated by discharge circuitry 503d, 514a,b.

Abstract: A synchronous buck converter having an improved transient response during output current stepdown. The device includes series and shunt MOSFETS, a first driver circuit to turn the series MOSFET on and off according to a variable duty cycle determined by an error signal representing the difference between the voltage output of the converter and a reference voltage, a sensing circuit operative to provide a control signal output when the duty cycle for the series MOSFET is zero; and a second drive circuit responsive to the control signal output of the sensing circuit to turn off the shunt MOSFET. The sensing circuit operates by detecting when the error signal is of a lower amplitude than the minimum value of the ramp waveform used to generate the duty cycle for the series MOSFET.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit using a filtering time delay in generating a detection signal with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time delay is controlled with the power transistor switching time.

Abstract: A voltage sequencer includes an input terminal and an output terminal and a control element connected between the input an output terminals. A capacitive element is connected between the output terminal and a first voltage and a resistive element is connected between the output terminal and a second voltage. The control element selectively controls charging and discharging of the capacitive element such that, upon the voltage at the input terminal increasing from the first voltage to a nominal value, the output terminal voltage increases to a nominal value in a first predetermined period of time and upon the voltage at the input terminal decreasing from the nominal value to the first voltage, the output terminal voltage decreases to the first voltage value in a second predetermined period of time, the first predetermined period of time being different from, for example, substantially greater than, the second predetermined period of time.

Abstract: A method and device are configured for providing for both quick and accurate signal settling. A high accuracy component is configured in parallel with a high speed component. The high accuracy component may be an op-amp. The high speed component may be an OTA that is configured to be a non-linear OTA. Furthermore, an ADC is configured to internally provide both quick and accurate signal settling. For example, an ADC comprises an internal high speed OTA configured in parallel with a connected external op-amp. The OTA is configured to be a non-linear OTA.

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: In a method for prescribing an essentially linear ramp with a prescribable slope by a quantity, and which is clock-pulse-controlled and which describes the ramp by an increment per clock interval, the ramp is described by a number of regular increments and by at least one first and one second irregular increment. The regular increments exhibit a value corresponding to the prescribable slope. The irregular increments exhibit a value deviating from the prescribable slope. The first irregular increment is a first increment describing the ramp and the second irregular increment is a last increment describing the ramp.

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract: An interface circuit includes a slew rate control unit 110, a pre buffer unit 120, and a main buffer unit 130. The slew rate control unit 110 is configured as a current source circuit of the pre buffer unit 120. The slew rate control unit 110 provides a constant current value by using a loop circuit which consists of a slew rate control macro 111, a decoder 112, a comparator 113, N transistor 114, an external terminal resistance (Rref) 115, and a reference voltage (Vref) 116. A size of the N transistor 114 is adjusted based on a code gradually changed in the loop circuit, and finally the current value is determined uniquely.

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A rectifier circuit produces an output which is a function of the magnitude of an input signal and has a controllable transient response. The circuit requires no rectification diodes. The voltage on a capacitor is sensed and compared with that of an input voltage. The operation of charging and discharging switches is adjusted by a control circuit to charge the capacitor if the magnitude of the input signal is greater than the capacitor voltage and to discharge the capacitor if the magnitude of the input signal is less than the capacitor voltage. The attack and release function of the rectifier is selectable by limiting the rate at which current charges/discharges the capacitor, preferably with constant current sources comprised of current mirrors. Multiple time constants are achieved by replicating the storage capacitor and charge/discharge elements configured with different time constants and then summing the resultant capacitor voltages.

Abstract: Method and system for providing a signal with a controllable zero crossing time value. The system provides first and second two-sided triangular wave signals, identical but shifted by a selected fraction f·T of a period T of either triangular signal, and forms a weighted sum of the signals, weighted by A and 1−A, respectively, with 0≦A≦1. In each of two time regions within a period T, a zero crossing time of the sum varies linearly with choice of the value A.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and a control signal. The second circuit may be configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and the control signal.

Abstract: An electric circuit configuration for shaping the slew rate of a pulsed output voltage occurring at an output terminal and for detecting a short circuit at the output terminal, having: a switchover control circuit for controlling the slew rate of the output voltage as a function of a voltage curve occurring across an internal resistor in a first switching state, and for feedback-controlling the slew rate as a function of the output voltage curve in a second switching state, and which is in a substantially dead state in a third switching state; a detector circuit which provides a detection signal when the output voltage differs by at least a predetermined value from the output voltage level occurring before edge onset; and a timer circuit for switching the control circuit from the first to the second switching state a predetermined length of time after edge onset if the detection signal is present at this time, and from the first to the third switching state if the detection signal is not present at this time.

Abstract: A signal transmission device including an input for receiving an input electrical signal containing a succession of pulses. The input signal has a high data rate, preferably in excess of 10 gigabits per second. The signal is split in two identical specimens, referred to as first signal and second signal and injected in respective channels of a lossy transmission path whose function is to carry the signals to an intended destination. Before introducing the second signal in the respective channel of the lossy signal transmission path, a negative DC shift is applied to the second signal. During the transmission of the first and the second signals through the lossy signal transmission path, they are subjected to distortions that cause the leading and the trailing edges of pulses in the signals to spread out. To compensate for this distortion, the first and the second signals are processed at the destination by first and second functional units that comprise non-linear signal transmission paths.

Abstract: A circuit and method are disclosed for controlling the slew rate of the output voltage of a driver in a push-pull configuration. The circuit includes a capacitive element and a current generator circuit for generating one or more currents. The circuit further includes a switching circuit for selectively charging and discharging the capacitive element in response to an input signal, wherein the voltage across the capacitive element is a voltage signal whose edge transitions have slopes which are controlled based upon the capacitance of the capacitive element and the current level of the one or more currents. The circuit further includes a conversion circuit for converting the voltage signal into one or more current signals, the one or more current signals being used to control a pull-up device and pull-down device of the driver so that the slopes of the edge transitions of the output voltage thereof is based upon the slopes of the edge transitions of the voltage signal appearing across the capacitive element.

Abstract: A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

Abstract: A DC--DC converter having an input node receiving an input voltage V.sub.IN and generating an output voltage V.sub.OUT. A reference voltage generator provides a voltage V.sub.REF and a hysteresis voltage generator provides a voltage V.sub.HYST. A first comparator generates a signal determined from a difference between V.sub.REF and V.sub.OUT. A second comparator generates a signal determined from a difference between V.sub.OUT and V.sub.HYST. A latch is coupled to receive the outputs of the first and second comparators, and to generate an output. A driver circuit receives the latch output and generates a PWM signal used to switch the output stage. A double pulse suppression circuit masks off the latch inputs for a preselected time during the switching intervals fo the main power transistors to eliminate noise jitter.

Abstract: A data communication receiving element includes a photo-receiving element for receiving an external light signal and for converting the light signal to a current signal. It further includes an amplifier circuit for amplifying the current signal after converting the current signal to a voltage signal. A waveform shaping circuit is included for shaping an output voltage waveform from the amplifier circuit to a substantially square pulse. Finally, an integrator is included for converting the substantially square pulse to a non-square pulse. This is achieved by extending a rising time necessary for shifting the substantially square pulse from a low potential level to a high potential level, and by extending a falling time necessary for shifting the substantially square pulse from the high potential level to the low potential level. As such, deterioration of an S/N ratio is suppressed.

Abstract: A battery-charging electronic device comprises a current generator adapted to supply a charging current to a battery and a controlled current edge switch having a circuit for controlling the switching edges of current being flowed through a power transistor. The switching edge control circuit comprises a controlled edge variable voltage generator for generating a controlled edge voltage signal, a voltage/current converter for converting the voltage signal to a controlled edge current signal, and a driver circuit for the power transistor being input the controlled edge current signal to mirror, onto the power transistor, an output current which is proportional to the controlled edge current signal.

Abstract: A circuit having multiple channels for generating multiple ramped voltage signals (preferably of a type useful in an interleaved PWM dc/dc converter) such that each ramped voltage signal has a different phase, and all the ramped voltage signals have a uniform controlled maximum amplitude. The circuit can be implemented as an integrated circuit (or portion of an integrated circuit) which generates the multiple ramped voltage signals with uniform maximum amplitude in a manner independent of process and temperature variations in implementing and operating such integrated circuit.

Abstract: A bus driver circuit for high speed data transmission includes a plurality of delay blocks connected in series one to another which varies a rise and fall time of an input signal in order to shape an output waveform. Each block includes one or more delay elements for providing a predetermined delay period. A selector input is provided for each delay block such that one or more of the predetermined delay periods can be selected. Hence, the rise and fall time of the input signal can be varied depending upon which block or combination of blocks have been selected to shape the resultant waveform. An output circuit is also included which superimposes the input signal on the resultant output waveform.

Abstract: A time-dependent piecewise linear signal generating circuit includes a first circuit responsive to a trigger signal to provide a number of time region signals each corresponding to a separate predefined time window of the piecewise linear signal, and a second circuit responsive to some of the time region signals to produce slope signals corresponding thereto, wherein each of the slope signals define a slope of the piecewise linear signal during a respective one of the time windows. A third circuit is responsive to the slope signals and the time region signals to produce the piecewise linear signal.

Abstract: Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.

Abstract: A ramp circuit repeatedly generates a substantially linear ramp signal. Ramp switch junction capacitance that otherwise causes a nonlinear output is compensated to improve signal linearity and enable faster retriggering. The ramp includes an output transistor, with its output coupled to a current source and a charge storage device. The output charge storage device charges when the transistor is on. When the transistor is turned off, the output charge storage device discharges, resulting in the changing ramp signal. The output transistor inherently includes a junction capacitance, which causes a nonlinearity in the discharge of the charge storage device. This nonlinearity appears as a quick drop in the ramp signal relative to the slower rate of steady-state decrease. This nonlinearity is prevented, however, by compensating for the output transistor's junction capacitance.

Abstract: A precision oscillator circuit having a wide adjustable operating frequency range and an adjustable duty cycle. The precision oscillator use a window comparator circuit for monitoring a voltage of a capacitive element. The window comparator circuit has a first operating voltage edge and a second operating voltage edge wherein the first operating voltage edge latches an output signal of the window comparator circuit at one level when the voltage of the capacitive element is greater than the first operating voltage edge. The second operating voltage edge brings the output signal of the window comparator circuit back to an initial level when the voltage of the capacitive element is greater than the second operating voltage edge. A precision current reference source is coupled to the capacitive element and to the window comparator circuit. The precision current reference is used for generating currents which are insensitive to temperature, supply voltage, and process variations.

Abstract: Slew-rate limited differential drivers are useful for reliable data transmission on longer un-terminated cables with longer stub lengths. Slew-rate limit can be achieved by the ratio of a constant current to a capacitor means. In order to have equal rise and fall times, an equal amount of current is steered into the capacitor means in opposite directions. This architecture has unequal propagation delays on the transition edges. This mismatch is directly attributable to the signal transfer in current steering means. The slew-rate limited differential driver corrects this problem by delaying the rising edge by the required amount using a second capacitor means and a diode means. And hence, the preferred embodiment has a better skew on the output.

Abstract: An amplification circuit is composed of a differential operational amplifier internally containing a current source circuit and having an inverted input connected to an output thereof through a parallel circuit composed of a first switch and a first capacitor. The inverted input is connected to one end of a second capacitor having the other end connected to a signal input terminal through a second switch. A non-inverted input of the differential operational amplifier is connected to a first reference voltage, and the other end of second capacitor is connected through a third switch to a second reference voltage.

Abstract: A circuit provides a duty cycle adjustment through a gate delay for operation at various output voltage levels. The delay may be provided through an OR gate and an AND gate that will generally modulate the duty cycle received at the input since most of the strength of the predriver resides in the pullup and pulldown transistors. The circuit may operate at a number of output voltage levels, including, but not limited to, CMOS and TTL levels. The implementation of the circuit also provides the advantage of parasitic load matching that may reduce EMI.

Abstract: A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver.

Abstract: A system for determining the time between the receipt of two different sils, includes a voltage ramp generator which generates a time dependent voltage signal upon receipt of a timing pulse at a time T.sub.1, and provides the instantaneous value of the voltage signal when the voltage ramp generator receives an input signal having a predetermined threshold value at time T.sub.2. A data processor coupled to receive the voltage signal, generates the timing pulse, and determines a time difference .DELTA.T from the voltage signal, where .DELTA.T=T.sub.2 -T.sub.1.