Abstract: A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Abstract: An improved system and method of determining the linearity of a ramp signal, including a ramp generator (11) for generating a ramp signal and a vernier delay (15) to provide scan stop signals where the samples are peak detected (17) and stored (21). The ramp generator (11) outputs are divided into equal sections controlled by a precise crystal controlled oscillator (25). The stored signals are processed and compared to detect errors.

Abstract: A degenerated differential pair waveform builder has a single ramp generator control circuit and a plurality of differential pairs. A trigger input is generated and input to the ramp generator control circuit. The ramp generator control circuit then generates a differential signal which is output to each of the differential pairs through a positive edge signal node and a negative edge signal node. Each differential pair then generates an output in response to the differential signal output from the ramp generator control circuit. The outputs from the differential pairs are combined in a summing circuit which outputs a composite waveform. Each differential pair has an associated ramp time which is dependent upon the value of the resistance in its emitter circuit. The ramp time of each differential pair directly affects the slope of its resulting output waveform.

Abstract: A graphics engine is disclosed which can be used in a color desktop publishing system. The graphics engine accepts 32-bit RGBM data and performs pixel level calculations under computer control to output processed 32-bit RGBM data The engine comprises a render processor interface, a run controller including a ramp generator, and a control unit. Interpolators are provided for each color (RGB) and cascaded with corresponding compositors. A transparency interpolator and matte combiner alter the matte plane of the video image. The engine can output data suitable for rendering by a color laser printer for a full size A3 page at 400 dots per inch.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: An integrated circuit pulse generator for per pin testing of electronic circuits. The pulse generator allows for independent adjustment of the slew rates of the rising and falling edges of the pulses. The pulse edges are generated by summing two separately controlled falling edge ramp generators. The circuit design of the pulse generator is structured to allow implementation with NPN transistors. The falling edge ramp generators operate by discharging a capacitor with a current source. The slew rates are varied by incrementally adding capacitance to the capacitor being discharged.

Abstract: An ultra-linear chirp generator includes a voltage controlled oscillator (VCO) having a tuning characteristic which is naturally nonlinear, a linear ramp generator which generates a linearly ramping output signal having a linear slope characteristic with respect to time, a polynomial correction waveform generator which generates a polynomial correction signal, and a summer which is responsive to and sums the linearly ramping output signal and the polynomial correction signal. The summer generates a VCO tuning signal for tuning the VCO. The tuning signal corresponds to the linearly ramping output signal predistorted with a nonlinearity opposite to the natural nonlinearity of the VCO tuning characteristic. The linear chirp generator also includes a phase locked loop which is responsive to the output signal of the VCO and which has a reference frequency which is related to the repetition rate of the output signal of the VCO.

Abstract: A circuit for dividing a reference current is composed of a number n of transistors connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node and by N+k (where k is an integer different from zero) directly biased diodes in series, connected between the generator and the fractionary current output node. The circuit does not employ current mirrors, so all transistors may have the minimum size, which also minimizes the effects of leakage currents. Additionally, compensation elements may be used for compensating the leakage currents from the base regions of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independence from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generator. Several embodiments are described.

Abstract: An asymmetrical ramp generator system for a pulse width modulator includes a complementary clock circuit; a first symmetrical dual ramp generator, responsive to the clock circuit, for generating first and second ramps having a predetermined voltage range and extending for a period equal to or greater than one half the clock cycle; a comparator device, responsive to the first and second symmetrical ramps and to a reference level within the predetermined voltage range of the first and second ramps, for generating corresponding dual first and second asymmetrical drive signals; and a second asymmetrical dual ramp generator, responsive to the first and second asymmetrical drive signals, for generating third and fourth asymmetrical overlapping ramps which extend beyond the predetermined voltage range.

Abstract: A level converter circuit has first and second P-channel transistors having the same first .beta. values, sources of the first and second P-channel transistors being commonly connected to a first potential V1, drains of the first and second P-channel transistors being connected to gates of the second and first P-channel transistors, respectively; first and second N-channel transistors having the same second .beta.

Abstract: Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A clock system and method for reducing the measured level of electromagnetic emissions, measured by a measuring device employing a C.I.S.P.R. quasi-peak detector from an electronic device having unintentional electromagnetic emissions at frequencies derived from a system clock is achieved by varying the frequency of the system clock in a range between first and second predetermined frequencies to spread the emission energy over the frequency range and reduce measured emission levels.

Abstract: A sawtooth oscillator includes a current source having an output coupled to a first capacitor for supplying it with a charge current (I). A discharge circuit discharges the first capacitor during a discharge period (TDS) in response to a voltage on the first capacitor. A second capacitor is coupled to the output of the current source. A switch interrupts the supply of charge current to the first capacitor during an interrupt period (TIS). Part of the charge current occurs during the discharge period (TDS). Subsequent to the interrupt period, the first capacitor receives a charge surplus built up by the charge current in the second capacitor. The current supply to the first capacitor is temporarily interrupted at least during a part of the discharge period. The second capacitor operates as an auxiliary capacitor in which a charge is stored which would otherwise have been supplied to the first capacitor.

Abstract: A method and apparatus of calibrating electronic scales for the horizontal axis of an oscilloscope is provided. For each of two electronic scales or cursors, output voltages of a horizontal deflection circuit are generated. A measurement is made to determine a time interval in which the voltage of a sweep waveform, generated by a sweep waveform generator and appearing at the output of the horizontal deflection circuit, passes the two output voltages. The slope of the sweep waveform generated by the sweep waveform generator is adjusted such that the time interval coincides with a target time interval.

Abstract: An apparatus for providing an EEPROM programming signal, comprises a charge pump circuit for receiving a programming input signal on a programming input line and for charging up a gate drive voltage signal in response to a rising edge of the programming input signal. A transistor that includes a gate coupled to the gate drive signal couples the programming input line to a programming output line, which is coupled to an EEPROM. A ramp control circuit including (i) a capacitor and (ii) a transistor controlling the flow of current through the capacitor, is coupled to the programming output line for regulating a ramp-up rate of a programming output signal on the programming output line. A ramp-down circuit is coupled to the programming input line and to the programming output line and is responsive thereto for providing a ramp-down of the programming output signal after the programming input signal goes low.

Abstract: A vertical ramp generator includes a voltage controllable charge current source and a switched discharge current source coupled across a ramp capacitor. A pair of comparators coupled to first and second reference potentials are supplied with the ramp capacitor voltage and drive a flip/flop, the output of which operates the discharge current source. A sync signal voltage is injected into the output of one of the comparators. Another comparator compares the ramp capacitor voltage with a third reference potential corresponding to the midpoint of the desired ramp voltage to control the switching of a pair of current sources that supply a square wave current to a correction capacitor which develops a DC correction voltage. The duty cycle of the square wave current is a function of the deviation of the ramp capacitor voltage from the third reference potential. The correction voltage controls the amount of current supplied by the charge current source.

Abstract: A slope compensation circuit for use with current-programmed switching DC to DC converters is provided which allows operation of the switching converters in the 1-2 MHz range. The circuit avoids feedback of an output voltage which includes the effects of a partially discharged slope capacitor without adding unnecessary delay by using a switch to bypass the discharging slope capacitor and coupling an input stage of the slope compensation circuit to an output driver. A delay in feeding back the output of the slope compensation circuit is provided to assure that the bypassing switch has settled.

Abstract: A television receiver is controlled as to the degree of vertical zoom via a deflection current ramp that varies in slope and which may be delayed to achieve panning. Due to the increased slope when zoomed, the deflection current and the electron beam complete a trace in less time than the normal vertical interval. The deflection current is maintained at one extreme or the other outside the trace interval, and the beam is blanked. A retrace signal generator coupled in a feedback loop with the power supply for the deflection circuit determines the midpoint of the blanking period and generates a fast retrace at or near the midpoint. The feedback loop is arranged to minimize the DC average current in the deflection winding by having a current source responsive to the DC average current for charging a timing ramp that triggers retrace upon reaching a threshold. The slope of the timing ramp varies with DC loading, thus advancing or retarding retrace to center retrace in the blanking interval.