Abstract: Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode.

Abstract: A power supply for providing power to devices in a network is described as incorporating an integral coupling feature that terminates the provision of power from an upstream power supply while maintaining connectivity of communications signals and ground from an upstream portion to a downstream portion of the network relative to the power supply. The power supply includes a logic feature that monitors a power status of an upstream power supply and/or its own power status. When the logic feature detects a power cycle, it initiates a coordinated power cycle of the associated power supply and/or other networked power supplies.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal.

Abstract: One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Abstract: The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

Abstract: In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

Abstract: A system and associated method is provided for improved rejection of an interfering signal coupled from a transmission antenna into a local receive antenna in the presence of local multipath. A system of the invention includes a common feedback junction, (i.e., a single sampling point used by all parameter matching control loops), for adjusting a number of distortion matching circuits while advantageously maintaining independence of tuning and other independent circuit actions.

Abstract: An integrated circuit device includes: an internal circuit; a ground terminal; a first terminal that is provided with a first signal that becomes to be a ground level during at least a portion of a period in which the internal circuit is operating; a detection circuit that compares a voltage on the first terminal and a voltage on the ground terminal, thereby detecting an open state of the ground terminal; and a setting circuit that sets the internal circuit to a reset state or a disabled state when the open state of the ground terminal is detected by the detection circuit.

Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.

Abstract: In a digital PLL frequency synthesizer, after lock detection, first oscillating signal phase information is switched to second oscillating signal phase information by an estimation section based on previous oscillating signal phase information and a phase difference. As a result, the first oscillating signal phase information which has a risk of an error in the normal state (locked state) is not used. In addition, a conventional high-speed latch circuit for reclocking is not required. As a result, power consumption can be reduced, compared to the conventional art, while reducing or avoiding a degradation in phase-noise characteristics.

Abstract: A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range.

Abstract: A phase-frequency detector includes an up signal generating unit and a down signal generating unit. The up signal generating unit is configured to evaluate a first node to generate an up signal, precharge the first node in response to a first clock, and reset the first node in response to the first clock, the up signal, and a down signal. The down signal generating unit is configured to evaluate a second node to generate a down signal, precharge the second node in response to a second clock, and reset the second node in response to the second clock, the up signal, and the down signal.

Abstract: An embodiment of the invention provides a clock calibration method to calibrate an internal clock signal of a computer. The method comprises: receiving an external clock signal from an external clock source; generating a pulse signal with a first duration according to the external clock signal; counting the internal clock signal according to the pulse signal to get a first count value; and calibrating the internal clock according to the first count value.

Abstract: A method and apparatus for providing system clock failover using a one-shot circuit are disclosed. A process, in one embodiment, is able to detect a clock failure using a one-shot circuit, wherein the clock signals are generated by a first clock circuit. Upon generating a switching signal in response to the clock failure, a system reset signal is asserted for a predefined time period in accordance with the clock failure. After switching a second clock circuit to replace the first clock circuit, the process is capable of resuming the clock signals via the second clock circuit.

Abstract: A resume and reset (RSMRST) signal output circuit, for outputting a low level voltage RSMRST signal, includes a first switch circuit, a delay circuit, and a second switch circuit. The first switch circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal it is when fully charged. The second switch circuit receives the second voltage signal and outputs the low level voltage RSMRST signal. The delay circuit is charged during a first state and discharged during a second state.

Abstract: A circuit for hot-swapping a memory card in an electronic device is disclosed. A power-reset unit has a first node electrically coupled to a power supply, and a second node electrically coupled to a power pin of the memory card. The power-reset unit is configured to generate a rising voltage at the second node without rebooting the electronic device when the memory card is hot-plugged into the electronic device.

Abstract: Provided is a semiconductor integrated device that selects one or more of a plurality of functional blocks and resets the selected functional block, and a control method of the semiconductor integrated device. The semiconductor integrated circuit includes a functional block that is reset when a clock signal and a reset signal are supplied, a reset signal output unit that outputs the reset signal for resetting the functional block, a clock mask circuit that stops the clock signal to be supplied to the functional block, and a clock mask control circuit that controls the clock mask circuit.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.

Abstract: A clock management unit includes a delay unit; and an output unit, wherein the delay unit receives a clock signal and a reset signal for resetting an external circuit, and supplies a delayed reset signal to the output unit, wherein the output unit supplies to the external circuit an external clock signal obtained by processing the clock signal and the delayed reset signal, and wherein the external clock signal does not experience any edge transitions during at least two periods of the clock signal after the reset signal transitions to an active state for resetting the external circuit.

Abstract: The invention relates to a method for activating the counter of a sectionalizer that allows the simultaneous opening of the phases of the sectionalizer since it includes for the radio transmission of the opening. According to the invention, the counter of the sectionalizer is activated upon detection of an increase in current over a given period greater than a pre-determined increase, allowing the sectionalizers to be standardized into a single model, as the counter is not activated using a threshold value, and allowing short-circuit currents to be differentiated from increases in current that are simply due to an increase in consumption.

Abstract: Provided is a startup circuit which allows a reference voltage generating circuit to start up and reach a stable equilibrium state in an extremely short period. The startup circuit is configured to hold voltage which is substantially the same as internal voltage of the reference voltage generating circuit in the stable equilibrium state even when power is not supplied to the startup circuit. The voltage is output from the startup circuit to the reference voltage generation circuit when the reference voltage generating circuit is started.

Abstract: Communication protocol methods for performing signal synchronization, data transmission, and data acknowledgement between a transmitting device and a receiving device are provided. The methods are characterized by a plurality of transmission lines which are used for performing signal synchronization, data transmission, and data acknowledgement by the communication protocol methods.

Abstract: A reset circuit includes two voltage dividing circuits, a switching circuit, a selection button, two voltage converters, and a processor. The voltage converters convert a first or second power supply for supplying power to the processor. When the first power supply supplies power to the processor the processor operates normally. When the second power supply supplies power to the processor, one of the voltage dividing circuits outputs a signal to the processor to restore an electronic device to factory settings according to the signal.

Abstract: A semiconductor memory apparatus includes a initialization signal generating unit configured to vary a voltage level of an external voltage in response to a detection signal, the external voltage enables a power-up signal, an internal voltage generating unit configured to produce an internal voltage, the internal voltage generating unit is initialized by the power-up signal, and a detection signal generating unit configured to produce the detection signal in response to a voltage level of the internal voltage.

Abstract: A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

Abstract: A method and apparatus of resetting a mobile device including a Power Management Integrated Circuit (PMIC) with no manual reset function are provided. The apparatus includes an input unit for creating a specific input signal for a reset according to a user's input. The apparatus includes a reset unit for creating a manual reset input signal in response to the specific input signal, and for blocking battery power supplied to the PMIC by using the manual reset input signal and a signal created during operations of the mobile device. The reset apparatus includes a power unit for supplying the battery power.

Abstract: Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component.

Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.

Abstract: A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.

Abstract: A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal.

Abstract: A voltage initialization circuit for recording a preferred voltage includes a first terminal, a second input terminal, a first buffer circuit connected to a first node, a second buffer circuit connected to a second node, a ground connected to the first buffer circuit via the first node and connected to the second buffer circuit via the second node, a first resistor, and a second resistor. The first resistor is connected between the first input terminal and ground. The second resistor is connected between the second input terminal and ground.

Abstract: A power supply voltage reset circuit, provided in an apparatus having an internal circuit capable of adjusting an internal power supply voltage, for resetting the internal circuit when a power supply voltage of the apparatus rises, and includes: a unit that generates an internal power supply voltage reference signal and changes a signal level thereof; a unit that generates an internal reference voltage to be a reference level in generating a reset signal for the internal circuit at a time of rising of the power supply voltage; a unit that generates a power-on adjustment voltage which rises later than the internal reference voltage at the time of rising of the power supply voltage and becomes greater than the internal reference voltage after a predetermined time passes; and a unit that generates the reset signal by comparing the internal reference voltage with the power-on adjustment voltage.

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract: A starting apparatus includes: a storage unit storing an identifier; a rectifying unit rectifying a reception signal; a generating unit comparing the reception signal rectified in the rectifying unit to a reference signal and generating a digital signal from the reception signal; a judging unit judging whether or not the digital signal contains information of the identifier; a reference changing unit changing the reference signal when the judging unit judges that the reception signal does not contain information of the identifier; and a start instructing unit instructing start of an electric appliance when the judging unit judges that the reception signal contains information of the identifier.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.

Abstract: A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks.

Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.

Abstract: Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (17) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter (19) (threshold voltage (Vtn) of an NMOS transistor (16)). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit (20). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit (10). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit (20).

Abstract: Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage detection circuit includes a Brokaw cell having a band-gap reference voltage, and a circuit portion for indicating the magnitude of an input voltage signal with respect to the band-gap reference voltage. The input voltage is applied to transistor bases of the Brokaw cell.

Abstract: An intelligent power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The intelligent power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Furthermore, the intelligent power-on reset circuit can include a processing element that is coupled to the programmable voltage divider. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent power-on reset circuit. The processing element can be for dynamically changing the programming during operation of the intelligent power-on reset circuit.

Abstract: A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.

Abstract: A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.

Abstract: A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.

Abstract: This application discloses a device that has a power-on reset generator. The power-on reset generator can include a power-on detector that receives an input electrical signal and outputs a digital signal that has predetermined value when the voltage of the input electrical signal exceeds a threshold voltage. The power-on detector can include multiple voltage-shaping elements arranged in series. Each voltage-shaping element can have a P-channel transistor and an N-channel transistor that differs in strength with respect to the P-channel transistor. The power-on detector can also include a switch that locks the digital signal at the predetermined value when the voltage of the input electrical signal exceeds the voltage threshold. In addition to the power-on detector, the power-on reset generator can include a digital delay that receives both the digital signal and a clock signal.

Abstract: A soft-start circuit is provided. The soft-start circuit comprises: an input stage, a pump stage, a second resistor and a capacitor. The input stage comprises a first resistor to receive an input voltage to provide a reference current at a first node. The pump stage comprises N current branches connected in parallel each comprising a current source connected to the first node and a switch to transfer the current from the current source to the second node while the switch operates in a connecting state. The switches has 2N connecting modes performed one after another to generate an output current with a gradual increment output current at the second node with 2N current levels; and the second resistor and the capacitor are connected in parallel between the second node and the ground potential to generate an output voltage with a gradual increment with 2N voltage levels according to output current.

Abstract: Methods for controlling a Power On Reset (POR) circuit in an Integrated Circuit (IC) are presented. In one embodiment, a method includes an operation for gating a test POR signal configured to selectively disable an output of a POR circuit, and an operation for programming a fuse. The programming of the fuse includes operations for disabling the signal path of the test POR signal, and for enabling the output of the POR circuit. In another embodiment, the signal path of the test POR signal includes a pass gate, where permanently disabling the signal path is performed by disconnecting the pass gate.

Abstract: A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor.