Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

Abstract: Systems and methods for cognitive thermal and power management of Information Handling Systems (IHSs) are described. In an illustrative, non-limiting embodiment, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: receive temperature information from a plurality of Power Supply Unit (PSU) thermal zones within an enclosure of the IHS, identify, based at least in part upon the temperature information, that a first PSU thermal zone is cooler than a second PSU thermal zone, or that the second PSU thermal zone is hotter than the first PSU thermal zone, and, in response to the identification, set a first PSU located in the first PSU thermal zone to active mode and set a second PSU in the second PSU thermal zone to standby.

Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: A digital Power on Reset (POR) circuit includes N counters; N comparators each connected to an output of a corresponding counter of the N counters to compare with a corresponding specific value, N is an integer greater than or equal to 1; and a comparison block connected to an output of each of the N comparators and configured to output a reset signal based on the output of each of the N comparators. The digital POR circuit utilizes a complete digital design, enabling efficient integration with a processing circuit. The digital POR circuit can utilize the same libraries, cells, etc. as other digital components in the processing circuit, and can be tested with other digital components in the processing circuit.

Abstract: The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: To provide a product-sum calculation device that includes a plurality of synapses including a transistor and having a variable resistance value, a plurality of input lines extending in a first direction and that propagates an input signal to each of the plurality of synapses, a plurality of output lines extending in a second direction orthogonal to the first direction, and that outputs a product-sum calculation result of the input signal from each of the plurality of synapses, and a charge and discharge control unit that controls an output state of the product-sum calculation result by controlling a charge and discharge state of the output line on the basis of a polarity of the transistor.

Abstract: An electronic circuit unit includes a trigger circuit and a circuit module. The trigger circuit includes a semiconductor switching element configured to output a switching pulse signal in response to an external trigger signal, a load resistor for the semiconductor switching element, a one-shot pulse circuit configured to convert the switching pulse signal into a one-shot pulse with a predetermined pulse width, and a forcible-reset circuit connected to an input side of the semiconductor switching element. The one-shot pulse circuit includes a coupling capacitor connected to an input side of the semiconductor switching element and a charging resistor for the coupling capacitor. The pulse width of the one-shot pulse is determined by a time constant of the coupling capacitor and the charging resistor. The forcible-reset circuit is configured to temporarily input an on-voltage to the semiconductor switching element so as to forcibly switch the circuit module to the operating mode.

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Abstract: A semiconductor chip includes a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when an output voltage is generated to have a voltage level of a ground voltage in a test mode, a charge discharge circuit configured to discharge charges of an output node that is included in a driving circuit when the discharge signal is enabled, and the driving circuit configured to generate the output voltage the voltage level of which rises up to a second set level by supplying charges from the external voltage to the output node in response to a driving signal a voltage level of which is decreased during an interval in which the voltage control signal is enabled.

Abstract: Disclosed is an operation method of a memory device which performs a self-refresh operation. The method includes receiving a deep-sleep mode enter command from a memory controller, changing a magnitude of an internal voltage of the memory device from a first voltage to a second voltage smaller than the first voltage, in response to the deep-sleep mode enter command, and entering a self-refresh mode under control of the memory controller, and the internal voltage is maintained at the second voltage during the self-refresh mode.

Abstract: A controller chip includes a first cluster including one or more first controller units, a first power supply grid, a first clock tree structure to supply one or more clock signals, and at least a first power supply input. A second cluster includes one or more second controller units, a second power supply grid, a second clock tree structure to supply one or more clock signals, and at least a second power supply input. A monitoring cluster includes a monitoring circuit configured to: monitor the power supply and the clock signal supply of each of the first cluster and second cluster, and in the event of determining at least one of a power supply failure or a clock signal supply failure in one cluster of the first cluster or the second cluster, indicate the failure to the other cluster to take one or more actions.

Abstract: A cryptocurrency miner includes a control power supply, a compute power supply, a compute module, and a controller. The compute module includes control circuitry powered based on first power supplied by the control power supply and a compute engine powered based on second power supplied by the compute power supply. The controller causes the control power supply to apply the first power to the control circuitry. The controller further causes the compute power supply to apply the second power to the compute engine after initialization of the control circuitry.

Abstract: A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.

Abstract: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.

Abstract: A voltage state detector includes a voltage drop circuit, a pull-down circuit, a load circuit, a transistor, a pull-up circuit, first and second output terminals, and a logic circuit. The pull-down circuit is coupled to the voltage drop circuit. The transistor has a first terminal coupled to the load circuit, a second terminal coupled to the pull-down circuit, and a control terminal coupled to the voltage drop circuit. The pull-up circuit is coupled to the load circuit and the voltage drop circuit. The first output terminal is coupled to the first terminal of the transistor for outputting a first state determination signal. The second output terminal is coupled to the voltage drop circuit for outputting a second state determination signal. The logic circuit includes a NOR gate for performing an NOR operation on the first state determination signal and the second state determination signal to output a control signal.

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

Abstract: An electronic device includes a hold circuit and a microcomputer. The hold circuit is connected to a power control line from a control device. The microcomputer starts measuring the time of a second state when the power control line transitions from a first state to the second state due to the control device. The microcomputer controls a power supply circuit to turn on power when the second state continues for a first predetermined time, and operates the hold circuit to maintain the power control line in the second state for a second predetermined time after the first predetermined time has elapsed.

Abstract: A circuit device includes a first power supply line to which a first power supply voltage is supplied, a second power supply line to which a second power supply voltage is supplied, a third power supply line, a power supply circuit, a predetermined circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When a first power-on reset signal and a second power-on reset signal become a reset release level, the reset control circuit sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level.

Abstract: A power on reset circuit comprises terminals for reference and supply potentials and a voltage divider coupled therebetween. First and second transistors of a bandgap circuit are resistively coupled to the reference potential terminal and have bases connected to the voltage divider. Current mirrors couple the collectors of the first and second transistors to an output terminal providing an output signal indicating a power on reset condition. A first compensation transistor is coupled between the collector of one of the transistors and the reference potential terminal, and a second compensation transistor is coupled between the output terminal and the reference potential terminal to compensate the effect of parasitic substrate currents in response to an external interference.

Abstract: A controller includes first and second half bridge sense circuits coupled to a half bridge node. The half bridge node is coupled between a high side switch and a low side switch coupled to an input. A rising slew detection circuit is coupled to the first half bridge sense circuit to output a first slew detection signal in response to a rising slew event at the half bridge node. A falling slew detection circuit is coupled to the second half bridge sense circuit to output a second slew detection signal in response to a falling slew event at the half bridge node. A control circuit coupled to output a high side drive signal to the high side switch and a low side drive signal to the low side switch in response to the first slew detection signal, the second slew detection signal, and a feedback signal.

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

Abstract: A printing apparatus includes a connector configured to receive supply of first power from outside, a switch circuit configured to supply the first power to a regulator, a latch circuit configured to control the switch circuit, a power switch configured to hold the latch circuit in a predetermined state, a controller configured to hold the latch circuit in the predetermined state and to detect an operation of the power switch, and a storage configured to store setting information. In response to supply of the first power to the connector, the latch circuit is configured to, when supplied with the first power and when the predetermined state is a first state, switch on the switch circuit to supply the first power to the regulator. The regulator is configured to generate second power based on the supplied first power and to supply the second power to the controller and the storage.

Abstract: An intelligent architecture system is provided. The intelligent architecture system includes an input line, an output line and an intelligent architecture operably interposed between the input line and the output line. The intelligent architecture is configured to control a voltage of the output line in accordance with a voltage of the input line.

Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of arrays, a number of power regulators, and a controller coupled to the non-volatile memory device. The arrays include a number of memory devices. A first array is determined to be in a non-responsive condition and a power regulator supplying power to the first array is instructed to cycle power to the first array. After the power to the first array has been cycled, a determination is made as to whether the first array is in a responsive condition.

Abstract: An electronic device includes a core circuit and a detecting circuit. The core circuit receives a first clock signal and a second clock signal that are different. The core circuit generates a first working state and a second working state respectively according to the first clock signal and the second clock signal. The detecting circuit detects a relationship between the first working state and the second working state to generate a reset signal. The reset signal is configured to reset the relationship between the first working state and the second working state to an initial corresponding relationship, and reduce an influence of electromagnetic interference on the electronic device.

Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

Abstract: A driver circuit and a display panel. The driver circuit comprises a driver chip (100), a detection signal generation circuit (200), and a feedback circuit (300). The detection signal generation circuit (200) is used for generating a detection control signal for performing aging detection according to the received first voltage signal and second voltage signal. The feedback circuit (300) is used for generating a feedback voltage and outputting same to the driver chip (100) according to the detection control signal and an working voltage, so that the driver chip (100) adjusts the outputted working voltage to a voltage required for performing the aging detection according to the feedback voltage, so as to satisfy the requirement for the diversity of voltage required for the voltage for the aging detection in the process of aging detection.

Abstract: An electrical power supply device is configured to communicate with a start-stop controller that automatically shuts down and restarts an internal combustion engine in a vehicle. The device includes a DC-DC power convertor and a device controller. The DC-DC power convertor is configured to produce a first voltage or a second voltage that is less than the first voltage. The device controller causes the DC-DC power convertor to produce the first voltage in response to a first signal from the start-stop controller indicating that the input voltage will remain equal to or greater than the threshold voltage and also causes the DC-DC power convertor to produce the second voltage in response to a second signal from the start-stop controller indicating that the input voltage may become less than the threshold voltage.

Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.

Abstract: A power providing circuit and a power providing method are provided. The power providing circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a signal latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to the first charge pump circuit and the at second charge pump circuit according to a power-on detection signal. The signal latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operation voltage and generate the power-on detection signal by detecting the operation voltage.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: One example charge pump is provided. The example charge pump includes a degeneration circuit, a charging current source transistor, a switch circuit and a discharging current source transistor. The charging current source transistor provides a charging current. The degeneration circuit is coupled between a first terminal of the charging current source transistor and a power supply terminal. The degeneration circuit degrades a first voltage corresponding to the power supply terminal to a second voltage. The switch circuit is coupled between a second terminal of the charging current source transistor and a load. The switch circuit controls a charging current output to the load.

Abstract: Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.

Abstract: A power-on reset circuit with reduced detection time. One example power-on reset circuit generally includes a voltage sensing circuit having an input coupled to a first power supply rail; a variable resistance component having a control input coupled to an output of the voltage sensing circuit and having a first terminal coupled to the first power supply rail; and an amplitude detection circuit having a first input coupled to the first power supply rail and having a second input coupled to a second terminal of the variable resistance component, the amplitude detection circuit being configured to generate a power-on reset signal at an output of the amplitude detection circuit based on a difference between a first voltage of the first power supply rail and a second voltage at the second terminal of the variable resistance component.

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

Abstract: A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.

Abstract: An organic light emitting diode display device includes a display panel including a plurality of sub-pixels, each of which includes a driving thin film transistor and a light emitting diode; and an impedance detection part connected to the plurality of sub-pixels of the display panel. The impedance detection part includes a sensing circuit part, an input control part, and an analog-to-digital converter. The input control part generates a modulated output by modulating an output of the sensing circuit part and inputs the modulated output to the analog-to-digital converter.

Abstract: An under voltage lockout circuit includes a reference circuit, an oscillator, a voltage divider, and a dynamic comparator. The reference circuit generates a reference voltage signal and a current source activation signal. The oscillator is activated to generate a clock signal after receiving the current source activation signal. The voltage divider samples an operating voltage signal to generate a detection voltage signal after receiving the clock signal. The voltage divider includes a switched-capacitor circuit for adjusting a ratio of the detection voltage signal to the operating voltage signal. The dynamic comparator receives the clock signal, the detection voltage signal and the reference voltage signal, and compares the reference voltage signal with the detection voltage signal only after receiving the clock signal. When the reference voltage signal is higher than the detection voltage signal, the dynamic comparator outputs a power-on-reset pulse signal.

Abstract: The invention discloses a flyback switching power supply, including a power input and rectifying circuit; a DC-DC switching circuit, the DC-DC switching circuit comprising a PWM control integrated circuit; and a voltage and current feedback circuit. The PWM control integrated circuit comprises a chip working frequency setting pin for setting a working frequency of the PWM control integrated circuit, the flyback switching power supply further comprises a frequency adjustment circuit connected between the chip working frequency setting pin of the PWM control integrated circuit and the voltage and current feedback circuit, and the frequency adjustment circuit is configured to decrease the working frequency when the flyback switching power supply is under a low load condition, and increase the working frequency when the flyback switching power supply is under a high load condition.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

Abstract: A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.

Abstract: A delay circuit includes a voltage/current conversion unit, a capacitor, and an output logic unit. The voltage/current conversion unit receives an input signal and generates current based on a voltage level of the input signal, and the generated current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage/current conversion unit and configured to receive the current generated by the voltage/current conversion unit, to charge. The output logic unit is electrically connected to the capacitor configured to receive a voltage signal on a terminal of the capacitor and generate an output signal based on the voltage signal, a delay time between a transition time point of the input signal and a transition time point of the output signal is not related to the voltage level of the input signal.

Abstract: A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.