Abstract: A driver circuit and a display panel. The driver circuit comprises a driver chip (100), a detection signal generation circuit (200), and a feedback circuit (300). The detection signal generation circuit (200) is used for generating a detection control signal for performing aging detection according to the received first voltage signal and second voltage signal. The feedback circuit (300) is used for generating a feedback voltage and outputting same to the driver chip (100) according to the detection control signal and an working voltage, so that the driver chip (100) adjusts the outputted working voltage to a voltage required for performing the aging detection according to the feedback voltage, so as to satisfy the requirement for the diversity of voltage required for the voltage for the aging detection in the process of aging detection.

Abstract: An electrical power supply device is configured to communicate with a start-stop controller that automatically shuts down and restarts an internal combustion engine in a vehicle. The device includes a DC-DC power convertor and a device controller. The DC-DC power convertor is configured to produce a first voltage or a second voltage that is less than the first voltage. The device controller causes the DC-DC power convertor to produce the first voltage in response to a first signal from the start-stop controller indicating that the input voltage will remain equal to or greater than the threshold voltage and also causes the DC-DC power convertor to produce the second voltage in response to a second signal from the start-stop controller indicating that the input voltage may become less than the threshold voltage.

Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.

Abstract: A power providing circuit and a power providing method are provided. The power providing circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a signal latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to the first charge pump circuit and the at second charge pump circuit according to a power-on detection signal. The signal latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operation voltage and generate the power-on detection signal by detecting the operation voltage.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: One example charge pump is provided. The example charge pump includes a degeneration circuit, a charging current source transistor, a switch circuit and a discharging current source transistor. The charging current source transistor provides a charging current. The degeneration circuit is coupled between a first terminal of the charging current source transistor and a power supply terminal. The degeneration circuit degrades a first voltage corresponding to the power supply terminal to a second voltage. The switch circuit is coupled between a second terminal of the charging current source transistor and a load. The switch circuit controls a charging current output to the load.

Abstract: Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.

Abstract: A power-on reset circuit with reduced detection time. One example power-on reset circuit generally includes a voltage sensing circuit having an input coupled to a first power supply rail; a variable resistance component having a control input coupled to an output of the voltage sensing circuit and having a first terminal coupled to the first power supply rail; and an amplitude detection circuit having a first input coupled to the first power supply rail and having a second input coupled to a second terminal of the variable resistance component, the amplitude detection circuit being configured to generate a power-on reset signal at an output of the amplitude detection circuit based on a difference between a first voltage of the first power supply rail and a second voltage at the second terminal of the variable resistance component.

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

Abstract: A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.

Abstract: An organic light emitting diode display device includes a display panel including a plurality of sub-pixels, each of which includes a driving thin film transistor and a light emitting diode; and an impedance detection part connected to the plurality of sub-pixels of the display panel. The impedance detection part includes a sensing circuit part, an input control part, and an analog-to-digital converter. The input control part generates a modulated output by modulating an output of the sensing circuit part and inputs the modulated output to the analog-to-digital converter.

Abstract: An under voltage lockout circuit includes a reference circuit, an oscillator, a voltage divider, and a dynamic comparator. The reference circuit generates a reference voltage signal and a current source activation signal. The oscillator is activated to generate a clock signal after receiving the current source activation signal. The voltage divider samples an operating voltage signal to generate a detection voltage signal after receiving the clock signal. The voltage divider includes a switched-capacitor circuit for adjusting a ratio of the detection voltage signal to the operating voltage signal. The dynamic comparator receives the clock signal, the detection voltage signal and the reference voltage signal, and compares the reference voltage signal with the detection voltage signal only after receiving the clock signal. When the reference voltage signal is higher than the detection voltage signal, the dynamic comparator outputs a power-on-reset pulse signal.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: The invention discloses a flyback switching power supply, including a power input and rectifying circuit; a DC-DC switching circuit, the DC-DC switching circuit comprising a PWM control integrated circuit; and a voltage and current feedback circuit. The PWM control integrated circuit comprises a chip working frequency setting pin for setting a working frequency of the PWM control integrated circuit, the flyback switching power supply further comprises a frequency adjustment circuit connected between the chip working frequency setting pin of the PWM control integrated circuit and the voltage and current feedback circuit, and the frequency adjustment circuit is configured to decrease the working frequency when the flyback switching power supply is under a low load condition, and increase the working frequency when the flyback switching power supply is under a high load condition.

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

Abstract: A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.

Abstract: A delay circuit includes a voltage/current conversion unit, a capacitor, and an output logic unit. The voltage/current conversion unit receives an input signal and generates current based on a voltage level of the input signal, and the generated current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage/current conversion unit and configured to receive the current generated by the voltage/current conversion unit, to charge. The output logic unit is electrically connected to the capacitor configured to receive a voltage signal on a terminal of the capacitor and generate an output signal based on the voltage signal, a delay time between a transition time point of the input signal and a transition time point of the output signal is not related to the voltage level of the input signal.

Abstract: A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.

Abstract: A welding device includes a laser irradiation unit that irradiates a workpiece with a laser light while scanning along an intended weld line of the workpiece, an upper jig arranged on a side of the laser irradiation unit with respect to the workpiece, and a lower jig arranged on an opposite side of the laser irradiation unit side. The upper jig includes an exposed portion that exposes the intended weld line of the workpiece to the laser irradiation unit side, an introduction path that is disposed in a downstream side in a scanning direction of the laser light and introduces an inert gas to the exposed portion, and a discharge path that is disposed in an upstream side in the scanning direction of the laser light and suctions the inert gas introduced to the exposed portion to discharge the inert gas to an outside.

Abstract: It is presented a power converter for transferring electric power provided on an input terminal to an energy storage element. The power converter comprises: an inductor; a switch connected to selectively control a connection between the inductor and the input terminal; and a comparator, wherein an output of the comparator controls the switch, a first input of the comparator is supplied with a voltage being proportional to a voltage of the input terminal, and a second input of the comparator is supplied with a voltage being proportional to a current from the input terminal; wherein the energy storage element is connected to a point between the inductor and the switch.

Abstract: The present disclosure relates generally to semiconductor devices, and, in particular, to monitoring circuitry configured to monitor a signal for an overcurrent, undercurrent, overvoltage, and/or undervoltage condition. The monitor circuit may utilize pull down transistors to generate a local voltage level. The local voltage level is then used to generate an indication of whether the monitored value has diverged from an operating region and/or has crossed a threshold of operation.

Abstract: A power on and power down reset circuit includes a reference voltage generation module, a monitoring voltage generation module, and a voltage comparator. The reference voltage generation module is utilized to generate a reference voltage with a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistance, and a second resistance. The monitoring voltage generation module is utilized to generate a monitoring voltage. The voltage comparator is utilized to generate a reset voltage by comparing the reference voltage to the monitoring voltage. Thus, the power on and power down reset circuit can achieve the effect of power savings and decreasing error rate of the reset voltage.

Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.

Abstract: Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: As a scanning line drive circuit of a display device, a shift register having a configuration in which a plurality of unit circuits are connected to each other in multiple stages is used. The unit circuits each include: a plurality of control transistors; an internal node connected to a terminal of one of the plurality of control transistors; and a depletion mode initialization transistor having a first conduction terminal connected directly or through a resistor to the internal node, a second conduction terminal, and a control terminal. One of a power supply voltage and a ground voltage is applied to the second conduction terminal, and the other voltage is applied to the control terminal. The initialization transistor is turned on in a power-off state.

Abstract: A power-supply detection-circuit control method is a method for a first microcomputer to control operation of a power-supply detection circuit, the first microcomputer being connected to the power-supply detection circuit and controlling a fan motor, the power-supply detection circuit detecting a voltage to be applied from a power supply to the fan motor, wherein the first microcomputer switches the power-supply detection circuit between an operating state and a non-operating state on the basis of information indicating whether a predetermined condition is satisfied.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: A voltage detection circuit includes a first transistor and a first resistor connected in series between a power supply voltage node and a reference voltage node, a second transistor and a second resistor connected in series between the power supply voltage node and the reference voltage node, a third transistor and a third resistor connected in series between the power supply voltage node and the reference voltage node, and a signal generator that outputs a signal corresponding to a voltage of a connection node between the third transistor and the third resistor. The second transistor is first turned on among the first to third transistors and a voltage level of the power supply voltage node increases, turning off the third transistor, and then a current flows through the first transistor and the first resistor. When the third transistor is turned on, the signal generator changes a logic of the signal.

Abstract: A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator generates a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilization circuit receives the power-on reset signal to keep a voltage level of the power-on reference voltage staying during a predetermined amount of time.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A power sequence monitoring system is disclosed, and comprises: a microprocessor and a control module. The microprocessor comprises a first conversion unit and a second conversion unit. The first conversion unit is used for converting a power-on signal received from a power management chip to a first digital signal, and the second conversion unit is adopted for converting a power-off signal received form the power management chip to a second digital signal. After receiving the first digital signal and the second digital signal from the microprocessor, and the control module outputs a plurality of power monitoring data to an electronic device, such that a user easily knows the power signal state of the host computer by the system of the present invention.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: An electronic device includes an interface with a first terminal, a second terminal, and a power supply. A voltage divider includes series-connected resistors, between the first terminal and ground voltage. A first programmable fuse is provided and the voltage divider converts the first signal to a different voltage level according to the state of the first programmable fuse. A first transistor has a gate receiving the converted first signal and a second transistor has a gate electrically connected to the second terminal and a source-drain terminal of the first transistor. The second transistor is off when the first transistor is on. A fuse-type switching element is connected between the power supply terminal a power supply circuit. A control terminal of the fuse-type switching element is connected to a source-drain terminal of the second transistor switches conduction state according to whether the second transistor is on or off.

Abstract: The present disclosure discloses a shift register and a driving method therefor, a gate drive circuit, and a display device. An input circuit is configured to respond to a signal of an input signal end and provide a signal of a first reference signal terminal to a first node; a reset circuit is configured to respond to the signal of the second node and provide a signal of a second reference signal end to the first node; and an output circuit is configured to respond to the signal of the first node and provide the signal of the clock signal end to an output signal end and is configured to respond to the signal of the third node and provide the signal of the second reference signal end to the output signal end.

Abstract: A device (1) for delivering a signal switching from a first state to a second state, comprising: a primary circuit (4) generating a primary signal; and a secondary circuit (6) configured to: when the primary signal is initialized to the second state upon power-up, initialize a ring counter (16) to a random value in a finite sequence including a reference value, change the value of the first ring counter (16) by running through the first finite sequence in a circular fashion, and deliver at an output (3): i) a secondary signal in the first state, when the value of the first counter is different from the reference value, and ii) the primary signal, when the value of the first counter is equal to the reference value.

Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.

Abstract: The disclosure provides a multi-voltage chip, including a regulator circuit, a high-voltage domain controller, a low-voltage domain controller, and a digital logic circuit. The regulator circuit receives and responds to a feedback signal, a regulating start signal, and a reference voltage to convert a system high voltage into a regulated voltage. The high-voltage domain controller receives a power signal and the system high voltage to provide the reference voltage and the regulating start signal. The low-voltage domain controller is coupled to the high-voltage domain controller and receives the regulated voltage to provide a system start signal in response to the regulating start signal. The digital logic circuit is coupled to the regulator circuit to receive the regulated voltage and provide the feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.

Abstract: A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.

Abstract: A circuit for generating a protection signal and a protection apparatus are provided. The circuit includes: a first flip flop, wherein the first flip flop is configured for receiving an enabling signal and an external signal input to the first flip flop and outputting a first level according to the enabling signal and the external signal; a second flip flop, wherein the second flip flop is in connection with the first flip flop and the second flip flop is configured for outputting a protection signal according to the first level and the external signal; and a feedback device, wherein the feedback device is connected between an output terminal of the second flip flop and an input terminal of the first flip flop and the feedback device is configured for outputting the enabling signal.

Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

Abstract: A power-on reset (POR) circuit includes first, second and third resistors. A first transistor has a first control terminal and first and second voltage terminals. A second transistor has a second control terminal and third and fourth voltage terminals. A third transistor has a third control terminal and fifth and sixth voltage terminals. The first control terminal is coupled via the first resistor to the second voltage terminal. The third voltage terminal is coupled via the second resistor to the first voltage terminal. The second control terminal is coupled via the third resistor to the fourth voltage terminal. The third control terminal is coupled to the third voltage terminal. The fifth voltage terminal is coupled to the first control terminal. A voltage buffer is coupled to the fifth voltage terminal.

Abstract: A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.

Abstract: A switching control circuit that controls switching of a switching device of a bridge circuit for driving a load. The switching control circuit includes a control circuit that outputs, on a signal line, a control signal at first and second logic levels for turning on and off the switching device based on a set signal and a reset signal, respectively, a setting circuit that is connected to the signal line, and that sets the logic level of the signal line to the second logic level for a period after the reset signal is inputted to the control circuit and before the set signal is inputted to the control circuit, a holding circuit that is connected to the signal line, and that holds the logic level of the signal line, and a drive circuit that is connected to the holding circuit, and that drives the switching device based on the output of the holding circuit.