Responsive To Power Supply Patents (Class 327/143)
  • Patent number: 10958159
    Abstract: Circuits and methods for providing at least a startup voltage for reversed-operation unidirectional power converters or bi-modal power converters sufficient to power at least an auxiliary circuit of such power converters while the normal supply voltage to at least the auxiliary circuit is insufficient to enable operation of the auxiliary circuit. Embodiments of the invention utilize an initial startup charge pump circuit to create a suitable startup voltage while the normal supply voltage to the auxiliary circuit is less than a specified voltage VMIN. Embodiments of the present invention also provide additional benefits, including small size since the initial startup charge pump circuit omits the use of an inductor, and high efficiency since the initial startup charge pump circuit may be disabled when the normal supply voltage to the auxiliary circuit is equal to or greater than VMIN.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 23, 2021
    Assignee: pSemi Corporation
    Inventors: David Andrew Kilshaw, Mark Moffat, Nigel David Brooke
  • Patent number: 10950283
    Abstract: A semiconductor device includes a latch signal generation circuit and a training result signal generation circuit. The latch signal generation circuit latches a first internal control signal and a second internal control signal to generate a first latch signal and a second latch signal. The first internal control signal is generated based on a first internal clock signal and a control signal, and the second internal control signal is generated. The training result signal generation circuit is synchronized with a first alignment pulse and a second alignment pulse generated based on the first latch signal and the latch signal, thereby generating a training result signal from the first and second latch signals.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10951209
    Abstract: A power on ready (POR) signal generating apparatus and an operation method thereof are provided. The POR signal generating device includes a detection circuit and a control circuit. The detection circuit detects a target voltage. When the target voltage is ready, the detection circuit sets a POR signal to a ready state. The control circuit is coupled to the output terminal of the detection circuit to receive the POR signal. After the POR signal transitions from a not ready state to the ready state, the control circuit maintains the POR signal in the ready state, and the control circuit disables the detection circuit.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 16, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Yu-Hsuan Liu
  • Patent number: 10924089
    Abstract: A comparing circuit and a comparing module with hysteresis are provided. The comparing module includes a first resistor, a second resistor, and the comparing circuit, which are electrically connected to each other. A comparison voltage is determined according to an input voltage and the resistances of the first resistor and the second resistor. The comparing circuit includes an input circuit, an eternal circuit, and a coupling module. The coupling module includes a first coupling transistor, a second coupling transistor, a third transistor, and a fourth coupling resistor. Control terminals of the first coupling transistor and the second coupling transistor are selectively electrically connected to either one of a first terminal and a second terminal. The second terminals of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to either one of the first terminal and the second terminal.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 16, 2021
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Xiao-Dong Fei, Wei Wang, San-Yueh Huang
  • Patent number: 10917075
    Abstract: An oscillator apparatus includes an oscillator circuit and a protection circuit. The oscillator circuit has an input and an output for generating a clock signal. The protection circuit is coupled to the input or the output of the oscillator circuit and is used for generating a second power switch control signal to the input of the oscillator circuit according to a signal edge of the clock signal and a first power switch control signal which is provided to the oscillator apparatus, to protect circuit element(s) included within the oscillator circuit.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Yi Chen
  • Patent number: 10897197
    Abstract: A switch-mode power supply and control circuitry that reduces variation in the switching frequency of the power supply with changes in loading. In one example, a switch-mode power supply includes an inductor, a transistor, and control circuitry. The transistor is coupled to the inductor, and configured to charge the inductor. The control circuitry is coupled to the transistor. The control circuitry is configured to turn off the transistor for a first time period. The first time period is a function of voltage across the inductor during the first time period. The control circuitry is also configured to determine whether the switch-mode power supply is operating in continuous conduction mode or discontinuous conduction mode. The control circuitry is further configured to add a predetermined fixed interval to the first time based on the switch-mode power supply operating in discontinuous conduction mode.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Yangwei Yu
  • Patent number: 10879891
    Abstract: A power supply voltage monitoring circuit includes a power supply switching circuit, a series circuit including a first series resistor connected to an input power supply line, a second series resistor connected to a ground potential, and a third series resistor connected between the first series resistor and the second series resistor, a first parallel circuit including a first switching element and connected in parallel to the first series resistor, a second parallel circuit including a second switching element and connected in parallel to the second series resistor, a first determination circuit configured to determine whether a first divided voltage between the first series resistor and the third series resistor is in a normal range, and a second determination circuit configured to determine whether a second divided voltage between the second series resistor and the third series resistor is in a normal range.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 29, 2020
    Assignee: JTEKT CORPORATION
    Inventor: Takanori Ito
  • Patent number: 10855261
    Abstract: Level-shifting circuits including a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices may be used to level-shift an input voltage signal between a low voltage domain having a low voltage level and a high voltage domain having a high voltage level, to obtain an output voltage signal having an output voltage level at an output node. A current-controlled tie circuit may be connected between the output node and the output voltage level, to conduct a current that causes the output node of the level-shifting circuit to be in a pre-defined logic state during a power-up sequence of the level-shifting circuit. Accordingly, spurious, non-deterministic output levels are avoided during the power-up sequence.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 1, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jianan Yang, James Nissen, David Wade Eickbusch
  • Patent number: 10848146
    Abstract: A reset circuit includes: an output circuit that outputs a reset release signal for releasing reset of a reset target circuit that is to be applied with a power supply voltage, when a first voltage that rises with a rise in the power supply voltage reaches a first reference voltage that rises with a rise in the power supply voltage until the first reference voltage reaches a target level; and an inhibit circuit that inhibits the reset release signal from being output to the reset target circuit until the power supply voltage reaches a third level, the third level being higher than a first level at a time when the first reference voltage exceeds the first voltage, the third level being lower than a second level at a time when the first voltage reaches the target level.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsuya Kawashima
  • Patent number: 10819334
    Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 27, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
  • Patent number: 10819333
    Abstract: A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ga-Na Kim, Po-Yun Park, Hong-Kyu Kim, Myeongsu Kim, Dongwon Park
  • Patent number: 10812070
    Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Giacomo Calabrese, Maurizio Granato, Giovanni Frattini
  • Patent number: 10797645
    Abstract: A circuit device has a first mode in which the circuit device outputs a clock signal and a second mode in which the circuit device does not output the clock signal. The circuit device includes an oscillation circuit, a non-volatile memory in which characteristic adjustment data of the oscillation circuit is stored, a reset circuit generating a reset signal, and a storage circuit into which the characteristic adjustment data is loaded from the non-volatile memory when the reset signal transitions from active to inactive. When the circuit device shifts from the second mode to the first mode, the reset circuit causes the reset signal to transition from active to inactive.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Shinnosuke Kano
  • Patent number: 10797688
    Abstract: A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Germano Nicollini
  • Patent number: 10788875
    Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 29, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Anup Nayak
  • Patent number: 10783420
    Abstract: A tag includes: a housing configured for coupling the tag to a physical object to organize activities regarding the physical object; and coupled to the housing: a wireless communication component; circuitry electrically coupled to the wireless communication component, the circuitry having a reset port and a switch port; a power source electrically coupled to the wireless communication component and the circuitry; a first switch between the power source and the reset port; a second switch between the reset port and ground, the second switch controlled by the switch port; and a capacitor between the reset port and the ground.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Adero, Inc.
    Inventors: Howard Friedenberg, Adrian Yanes, Kristen Johansen, Jack J. Shen, Siddharth S. Sahu, Nathan Kelly
  • Patent number: 10763815
    Abstract: According to one embodiment, an IC chip includes a plurality of fuse elements including a plurality of fuse portions each of which is to be cut off by a stress, and a plurality of actuator portions provided for the plurality of fuse portions, respectively, and each of which applies a stress to corresponding one of fuse portions, and a control circuit supplying a control signal for cutting off desired one of the fuse portions to corresponding one of the actuator portions.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 1, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tamio Ikehashi, Hiroaki Yamazaki
  • Patent number: 10763835
    Abstract: A semiconductor apparatus includes a first voltage detection circuit configured to generate a first voltage detection signal in response to the voltage level of a first voltage, a current control signal and a second voltage detection signal; and a storage and output circuit configured to generate a power control signal and the current control signal in response to the voltage detection signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10763848
    Abstract: A gate drive circuit includes a signal generation unit configured to generate a first gate drive signal, a signal isolation unit configured to produce, at an output side thereof in response to the first gate drive signal, a second gate drive signal electrically isolated from the signal generation unit, an output stage device configured to receive the second gate drive signal at an input side thereof and to produce a third gate drive signal at an output side thereof in response to the second gate drive signal, a first path connecting the output side of the signal isolation unit and the input side of the output stage device; and a second path connecting the output side of the signal isolation unit and the output side of the output stage device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 1, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Sho Takano, Hidetoshi Umida
  • Patent number: 10756565
    Abstract: According to aspects of the disclosure, a method and system are provided for transferring a load between a primary power source and a secondary power source. In accordance with the disclosure, a method of transferring a load between a first power source and a second power source includes analyzing a plurality of power sources to identify one or more power sources providing a power greater than a threshold value. The method also includes selecting a power source from the identified one or more power sources providing power greater than the threshold value. The method further includes connecting the selected power source to a transfer mechanism. The method still further includes actuating the transfer mechanism, using power provided to the transfer mechanism by the selected power source, to transfer the load from a connection with the first power source to a connection with the second power source.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 25, 2020
    Assignee: ASCO POWER TECHNOLOGIES, L.P.
    Inventor: John E. Hayes
  • Patent number: 10719106
    Abstract: A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ruhong Zhang, Jinbo Ding, Zhengsheng Xie
  • Patent number: 10712807
    Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Harshat Pant, Rajeev Jain, Byron Glenn Murphy, Lipeng Cao
  • Patent number: 10715120
    Abstract: A semiconductor apparatus includes a first voltage detection circuit configured to generate a first voltage detection signal in response to the voltage level of a first voltage, a current control signal and a second voltage detection signal; and a storage and output circuit configured to generate a power control signal and the current control signal in response to the voltage detection signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10714195
    Abstract: A system includes memory cells arranged in blocks and a memory controller. The memory controller receives a read command to read a first block. The first block can be associated with a first read count and a first read threshold. The first read count is incremented when the first block is read, and when the first read count reaches the read threshold, a read reclaim test is performed. The first read count is set to zero after a power off or a read reclaim operation. When the first read count is zero, an adaptive read threshold is selected based on the number of bit errors. Further, in a read reclaim test, the number of bit errors is tested against an adaptive error threshold to determine whether a garbage collection operation is performed.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 14, 2020
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Fan Zhang, Chenrong Xiong, Yu Cai
  • Patent number: 10707863
    Abstract: A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 7, 2020
    Assignee: LONTIUM SEMICONDUCTOR CORPORATOIN
    Inventors: Jiaxi Fu, Cheng Tao, Xiangyu Ji, Feng Chen
  • Patent number: 10686437
    Abstract: A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at an output node and the fourth current terminal couples to a ground node. A third transistor includes a third control input and fifth and sixth current terminals. The fifth current terminal couples to the output node and the sixth current terminal couples to the ground node. A fourth transistor includes a fourth control input and seventh and eighth current terminals. The eighth current terminal couples to the ground node and the seventh current terminal couples to the third control input. An inverter having an input coupled to the second control input and an output coupled to the fourth control input.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Patent number: 10672453
    Abstract: The present disclosure provides a charge pump system and a method of operating the same. The charge pump system includes a first pump circuit, a second pump circuit and a control device. The first pump circuit is configured to operate in a first voltage domain. The second pump circuit is configured to operate in a second voltage domain different from the first voltage domain. The control device is configured to selectively enable one of the first pump circuit and the second pump circuit based on an operating environment, wherein the one of the first pump circuit and the second pump circuit provides a pump voltage.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 2, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10666249
    Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon Na, Seon Kyoo Lee, Jeong Don Ihm, Byung Hoon Jeong, Young Don Choi
  • Patent number: 10642303
    Abstract: A method for fast-enabling a current source includes conducting a first current through a first branch including a first transistor connected in series with a first switch, in response to enabling the first switch with an enable signal. A first charge is removed from a bias rail with a first capacitance between a first gate and a first source of the first transistor. A second current is conducted through a second branch including a second switch connected in series with a second transistor, in response to enabling the second switch with the enable signal. A second charge is added to the bias rail with a second capacitance between a second drain and a second gate of the second transistor, wherein the first gate and the second gate are connected to the bias rail and biased by the mirror reference voltage.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: May 5, 2020
    Assignee: NXP USA, Inc.
    Inventors: Ondrej Pauk, John Pigott
  • Patent number: 10630102
    Abstract: The embodiments described herein provide a battery solution for electronic devices that addresses one or more of the above discussed defects. More specifically, a battery device is provided and capable of uninterruptedly supplying power to an electronic device, even when the rechargeable battery in the electronic device is removed. The battery device according to the various embodiments herein can have a host battery and a main battery, each operable to independently supply power to the electronic device in order for the electronic device to carry out its normal operation. When the main battery is removed from the electronic device, the host battery remains in the electronic device and operates to supply power thereto, so that the electronic device can continue its normal manner without interruption, thereby avoiding power shutdown and rebooting operation of the electronic device.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: April 21, 2020
    Inventor: Shuang Sa
  • Patent number: 10620267
    Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Srinivas Dhulipalla
  • Patent number: 10601406
    Abstract: A semiconductor apparatus includes a first voltage detection circuit configured to generate a first voltage detection signal in response to the voltage level of a first voltage, a current control signal and a second voltage detection signal; and a storage and output circuit configured to generate a power control signal and the current control signal in response to the voltage detection signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Sk hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10566973
    Abstract: Sending, receiving and transmitting apparatuses of a dual-power system and a fingerprint recognition system are provided. The dual-power system includes a first power system for providing a first high voltage signal and a first low voltage signal and a second power system for providing a second high voltage signal and a second low voltage signal, and a voltage difference between the first high voltage signal and the first low voltage signal is equal to that between the second high voltage signal and the second low voltage signal. The sending apparatus includes a first detection circuit for outputting a detection signal indicating whether voltages of the first and second low voltage signals are equal; and a first transmission circuit for transmitting an output signal of the dual-power system or provide a first voltage to an output terminal of the sending apparatus, based on the detection signal.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: February 18, 2020
    Assignee: FOCALTECH ELECTRONICS, LTD.
    Inventors: Yunn-Hwa Wang, Kuet Liong Fam
  • Patent number: 10566969
    Abstract: An electrical reset circuit is configured to generate a reset pulse to reset one or more electrical components. The electrical reset circuit includes a first device electrically connected between a power supply input and a first node. The first device is configured to conduct current after the power supply input reaches a first voltage threshold. The electrical reset circuit also includes a second device electrically connected between the power supply input and a second node, where the second device is configured to conduct current after the power supply input reaches a second voltage threshold. In some examples, the electrical circuit includes a delay circuit configured to delay the reset pulse. Corresponding methods to providing a reset pulse are also contemplated.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 18, 2020
    Assignee: ROLLS-ROYCE CORPORATION
    Inventor: John Joseph Costello
  • Patent number: 10516393
    Abstract: A power on reset circuit includes a first inverting circuit, a second inverting circuit, a charging apparatus, an output buffer, a current drainer, and a first capacitor. The first inverting circuit and the second inverting circuit are coupled between a voltage detection end and a signal control end in opposite directions. The current drainer drains a current from the voltage detection end according to a power voltage and a voltage on the signal control end. The charging apparatus charges the voltage detection end according to the voltage on the signal control end. The output buffer generates a reset signal according to the voltage on the signal control end.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Jyun-Yu Lai, Hsing-Yu Liu
  • Patent number: 10515705
    Abstract: A sensing circuit includes a plurality of cascode transistors including: a Flash memory cell; a sensing node; and an NMOS. The sensing circuit further includes a charge pump for generating an output voltage. A first output voltage is directly input to the plurality of cascode transistors during programming, and a second output voltage of the charge pump is coupled to a gate of the NMOS during a read to bias the NMOS. A sensing amplifier has an input coupled to the sensing node for receiving read data of the Flash memory cell when the NMOS is biased. A low-pass filter is coupled between the second output voltage of the charge pump and the gate of the NMOS.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: December 24, 2019
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan Tang, Jen-Tai Hsu
  • Patent number: 10505534
    Abstract: An integrated circuit includes an enable circuit and a main circuit. The enable circuit is configured to receive a supply voltage and an enable signal at a first voltage level, generate a start voltage by clamping the supply voltage to a threshold voltage level that is less than the supply voltage and generate an enable intermediate signal at a second voltage level that is less than the first voltage level and limited by the start voltage. In response to the enable intermediate signal being generated at the second voltage level, the enable circuit is configured to generate a start signal (such as a current). In response to the start signal being generated, the enable circuit is configured to generate an output signal at a third voltage level that is less than the first voltage level. The main circuit is configured to utilize the output signal as a supply voltage rail.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Faruk Jose Nome Silva, Tawen Mei, Karen Chan
  • Patent number: 10496414
    Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Chul Moon Jung, Joo Hyeon Lee, Sung Nyou Yu
  • Patent number: 10469074
    Abstract: A power on/off reset circuit includes a driving circuit, a hysteresis control circuit and a buffering circuit. The driving circuit detects a first level of a power supply voltage during a power-on duration of the power supply voltage, detects a second level of the power supply voltage during a power-off duration of the power supply voltage, and generates a driving signal that is transitioned based on the first level and the second level. The hysteresis control circuit is connected to an output terminal of the driving circuit, is activated or deactivated based on the power supply voltage without a control signal, is activated during one of the power-on duration and the power-off duration, and is deactivated during the other of the power-on duration and the power-off duration. The buffering circuit is connected to the output terminal of the driving circuit, and generates a reset signal based on the driving signal.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Kim, Yong-Joo Song
  • Patent number: 10432192
    Abstract: A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Divya Kaur, Rajat Chauhan, Vipul Kumar Singhal
  • Patent number: 10418099
    Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Inuzuka, Tsuneo Inaba, Takayuki Miyazaki, Takeshi Sugimoto
  • Patent number: 10355692
    Abstract: The present technology relates to a semiconductor device that includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block. Further, the power source monitoring circuit is provided with a transistor on a path of a steady-state current, and the steady-state current is inhibited from flowing in accordance with the standby control signal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventor: Yuki Yagishita
  • Patent number: 10348113
    Abstract: An electronic apparatus including a power supply circuit and an electronic apparatus body is provided. The power supply circuit includes a power input port, a first power circuit, a battery module, a reset circuit and a second power circuit. The power input port receives an input power. The first power circuit converts the input power and outputs a first power to charge the battery module. The reset circuit generates a reset pulse signal responding to that the input power starts to be provided. The battery module is controlled by the first power circuit to provide the first power to the second power circuit if the input power is not provided. The second power circuit converts the first power, accordingly provides an output voltage signal to the electronic apparatus body, and resets the electronic apparatus body by disabling the output voltage signal responding to the reset pulse signal.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: July 9, 2019
    Assignee: CAL-COMP BIG DATA, INC.
    Inventor: Min-Hsin Lin
  • Patent number: 10340912
    Abstract: A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 2, 2019
    Assignee: CSMC Technologies FAB2 Co., Ltd.
    Inventor: Yun Gao
  • Patent number: 10333511
    Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Alexander Wayne Hietala, Christopher Truong Ngo, Praveen Varma Nadimpalli
  • Patent number: 10334688
    Abstract: Embodiments of the present disclosure involve a detection circuit for a tube and a tube including the detection circuit. The detection circuit comprises: impedance connected between two ends of a tube; a voltage detector configured to detect voltage on the impedance; a voltage threshold circuit configured to provide a voltage threshold; a first control circuit configured to compare voltage across the two ends of the tube to the voltage threshold, and to control the voltage detector to detect only when the voltage across the two ends of the tube is smaller than the voltage threshold. By using the detection circuit of the present disclosure, it can detect whether a human body contacts the tube under protection state, to avoid of the risk of getting an electrical shock.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 25, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Han Lu, Jingxu Zhou, DeYong Kong
  • Patent number: 10331204
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Patent number: 10311803
    Abstract: Provided is a backlight driving circuit, comprising voltage conversion circuit, PMW controller, zener diode, first electrical switch, optocoupler unit, boost switch and light source drive assembly. The PMW controller controls an output of the voltage conversion circuit. The light source drive assembly is connected to the boost switch and a light source to control on and off of the boost switch. A cathode of the zener diode is connected to the optocoupler unit, and an anode of the zener diode is connected to a control end of the first electric switch, and a first end of the first electrical switch is connected to the PWM controller, and a second end of the first electrical switch is grounded, and as the boost switch is short, a current outputted by the voltage conversion circuit increases, and the optocoupler unit breaks the zener diode down.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 4, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Wendong Li
  • Patent number: 10256810
    Abstract: Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues outputting the initialization control signal at the first level until the clock signal is output; and when the initialization state hold signal is input and the clock signal is output, outputs the initialization control signal at the second level cancelling the initialization process to the initialization circuit.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 9, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Akira Shirao
  • Patent number: RE47832
    Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 28, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERISSON (PUBL)
    Inventors: Tarmo Ruotsalainen, Joni Tuomas Jäntti