With Delay Means Patents (Class 327/153)
  • Patent number: 10422830
    Abstract: A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing ring oscillator (2) consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (2). The number of oscillations of the self-timing ring oscillator (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 24, 2019
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weiwei Shan, Longxing Shi, Jun Yang
  • Patent number: 10425070
    Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 24, 2019
    Assignee: GSI Technology, Inc.
    Inventors: Yu-Chi Cheng, Patrick Chuang, Jae-Hyeong Kim
  • Patent number: 10389335
    Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 20, 2019
    Assignee: Apple Inc.
    Inventors: Steven F. Schicht, William R. Weier
  • Patent number: 10249353
    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Lei Luo
  • Patent number: 10095263
    Abstract: Aspects of the disclosure include a data storage controller that includes a main circuit, a synchronization circuit, and a detection circuit. The main circuit is configured to receive a test signal, generate a data signal based on the test signal, and generate a compensation signal based on the test signal and a phase shift selected from N predetermined phase shifts. N may be an integer greater than one. The synchronization circuit is configured to receive the data signal and the data compensation signal, and generate a delayed data signal and a latched compensation signal in response to the data signal. The detection circuit is configured to determine whether rising and falling edges of the latched compensation signal and corresponding rising and falling edges of the delayed data signal are synchronized.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 9, 2018
    Assignee: Marvell International Ltd.
    Inventors: Kai Wu, Yunfan Zhang
  • Patent number: 9894628
    Abstract: A clock circuit includes a selector circuit connected to an output terminal, first, second, and third paths connected in parallel between an input terminal for receiving an input clock signal and the selector circuit, a first clock signal output from the first path being delayed with respect to a second clock signal output from the second path by a predetermined length of time, and the second clock signal being delayed with respect to a third clock signal output from the third path by the predetermined length of time, and a control circuit configured to control the selector circuit to switch among at least two of the first, second, and third clock signals.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yosuke Ogasawara
  • Patent number: 9882709
    Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: January 30, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart R. Zeydel
  • Patent number: 9876668
    Abstract: To enable a large-capacity, high-quality data communication that is excellent in bit error rate characteristic even in an adverse noise environment mainly caused by phase noises or thermal noises. [Solution] Included are: a first phase error detection filter that generates, on the basis of a forward sequence of received symbols, a first phase difference value and a first phase error estimated value; a second phase error detection filter that generates, on the basis of a backward sequence of received symbols, a second phase difference value and a second phase error estimated value; a phase error combination means that generates a third phase error estimated value on the basis of the first and second phase error estimated values and one of the first and second phase difference values; and a phase error compensation means that compensates the phase error of the received symbols in accordance with the third phase error estimated value.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: January 23, 2018
    Assignee: NEC Corporation
    Inventors: Norifumi Kamiya, Eisaku Sasaki
  • Patent number: 9853633
    Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 26, 2017
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Yu-Chi Cheng, Patrick Chuang, Jae-Hyeong Kim
  • Patent number: 9804225
    Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 31, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Saurabh Kumar Singh, Balwant Singh
  • Patent number: 9685141
    Abstract: A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sanquan Song, Wei Xiong
  • Patent number: 9448281
    Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jinn-Yeh Chien, Yung-Chow Peng, Chung-Chieh Yang, Kuan-Yu Lin
  • Patent number: 9378786
    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 28, 2016
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Lei Luo
  • Patent number: 9018990
    Abstract: A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 28, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ye Liu
  • Patent number: 9000814
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • Patent number: 8983012
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8976619
    Abstract: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Tokuhiro
  • Patent number: 8976054
    Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
  • Patent number: 8963597
    Abstract: A cross-domain enablement method is configured for providing a local clock signal to a logic-circuit device, which is operated in a delay-locked loop (DLL) domain. The logic-circuit device includes a command input and a clock input. The cross-domain enablement method comprises steps of: starting to provide the local clock signal to the clock input of the logic-circuit device by enabling a clock signal in the DLL-domain when a first command signal in a clock domain is activated; and, providing a second command signal in the DLL-domain to the command input of the logic-circuit device. The second command signal in the DLL-domain is activated later than the first command signal in the clock domain.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Nanya Technology Corporation
    Inventor: Kallol Mazumder
  • Patent number: 8957736
    Abstract: The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 17, 2015
    Inventor: Akira Takizawa
  • Patent number: 8957714
    Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Jan Christian Diffenderfer, Philip Michael Clovis, David Ian West
  • Publication number: 20150042388
    Abstract: A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.
    Type: Application
    Filed: November 11, 2013
    Publication date: February 12, 2015
    Applicant: SK hynix Inc.
    Inventors: Ji Seop SONG, Chang Kyu CHOI
  • Patent number: 8947141
    Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Publication number: 20140312941
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 23, 2014
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • Patent number: 8860476
    Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 14, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
  • Patent number: 8847641
    Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 30, 2014
    Assignee: MegaChips Corporation
    Inventor: Shoichiro Kashiwakura
  • Publication number: 20140281652
    Abstract: A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Tukaram Shankar Methar, Nilesh Acharya, Jyotirmaya Swain, Brian Lawrence Smith
  • Publication number: 20140266336
    Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: SILICON LABORATORIES INC.
    Inventors: Imranul Islam, Axen Thomsen, Paul I. Zavalney
  • Patent number: 8829957
    Abstract: A clock signal from a first electronic subsystem is distributed to a second electronic subsystem. The second electronic subsystem is remote from the first electronic subsystem and coupled to the first electronic subsystem by a bidirectional signal path. A first clock signal is generated on the first electronic subsystem and a training signal is generated on the first electronic subsystem clocked by the first clock signal. The training signal is sent on the bidirectional signal path on a round trip to the second electronic subsystem and back to the first electronic subsystem. A phase of the training signal is adjusted symmetrically on the way to the second electronic subsystem in a first phase adjuster and on the way back to the first electronic subsystem in a second phase adjuster until the measured time for the round trip is equal to an even number of clock cycles.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: September 9, 2014
    Assignee: PRO DESIGN Electronic GmbH
    Inventors: Sebastian Fluegel, Dragan Dukaric
  • Patent number: 8823431
    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Min Jang, Yong Ju Kim, Dae Han Kwon, Hae Rang Choi
  • Patent number: 8782460
    Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group, where the data bit signal is transmitted by a transmitting device along with a data strobe signal. The synchronous receiver receives the data bit and the data strobe signals, and includes a delay-locked loop (DLL). The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal, and where the delayed bit signal is delayed relative to the data strobe signal by the amount, thus allowing for proper reception of the data bit signal.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 15, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Darius D. Gaskins, James R. Lundberg
  • Publication number: 20140184288
    Abstract: Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hee KIM, Ju-Hyun KANG, Dong-Youb KIM, Min-su KIM, Sun-Gyeum KIM, Uk-Rae CHO, Sang-Shin HAN
  • Patent number: 8766646
    Abstract: An embodiment of the invention provides a clock calibration method to calibrate an internal clock signal of a computer. The method comprises: receiving an external clock signal from an external clock source; generating a pulse signal with a first duration according to the external clock signal; counting the internal clock signal according to the pulse signal to get a first count value; and calibrating the internal clock according to the first count value.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 1, 2014
    Assignee: Nuvoton Technology Corporation
    Inventors: Kuofeng Li, Wen Pin Chu, Yueh-Yao Nain
  • Patent number: 8769330
    Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: July 1, 2014
    Inventor: Adam Kaiser
  • Patent number: 8736384
    Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Ofir Degani, Hasnain Lakdawala, Masoud Sajadieh
  • Publication number: 20140139276
    Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 22, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: William J. Dally
  • Patent number: 8729937
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • Patent number: 8729941
    Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Patent number: 8729940
    Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Jun Ku
  • Patent number: 8731125
    Abstract: The present invention discloses a method and apparatus for aligning the phases of a master clock and a slave clock; and the method comprises the following steps: A. locking a phase of a master clock; B. measuring phase difference between a slave clock and the master clock; and C. adjusting a phase output by the slave clock so as to align it with the phase of the master clock based on the phase difference measured in Step B. The present invention also discloses an apparatus for aligning the phases of a master clock and a slave clock. By measuring the phase difference between the master clock and the slave clock, and aligning the phases of the master clock and the slave clock according to the phase difference the present invention improves the precision of phase alignment without increasing costs.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 20, 2014
    Assignee: ZTE Corporation
    Inventor: Shan Zhong
  • Publication number: 20140132317
    Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
  • Patent number: 8704561
    Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: April 22, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hye-Young Lee, Yong-Mi Kim
  • Patent number: 8704560
    Abstract: A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 8707001
    Abstract: Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: April 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Nan Chen, Zhiqin Chen, Varun Verma
  • Patent number: 8683253
    Abstract: An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to advance a synchronous data strobe associated with a data group. The transmitting device has a core clocks generator and a synchronous strobe driver. The core clocks generator advances a data strobe clock by the amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe is advanced also by the amount. The receiving device has a composite delay element and delay-locked loops (DLLs). The composite delay element equalizes delay paths within the receiving device, where the delay paths correspond to the synchronous data strobe that is received from the transmitting device.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: March 25, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Darius D. Gaskins, James R. Lundberg
  • Publication number: 20140035636
    Abstract: A method of synchronizing clock signals may include generating a replicated delay associated with a delay of a clock signal path. The clock signal path may be associated with communication of a slave clock signal by a master block of a circuit to a slave block of the circuit. The method may further include selecting the slave clock signal from one of multiple clock signals based on the replicated delay. Each of the multiple clock signals may have a same frequency and a different phase.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Asako TODA
  • Patent number: 8643413
    Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 4, 2014
    Inventors: Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
  • Patent number: 8638137
    Abstract: A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Il Chung
  • Patent number: 8620605
    Abstract: A method for detecting and determining a position of faults using reflectometry in a wired electrical network including: injecting a test signal e(t) into a cable in the electrical network, a timing of successive injections being controlled by a synchronization module that generates an emission clock signal and a reception clock signal; retrieving a reflected signal on the cable; sampling the reflected signal at a frequency Fe=1/Te, where Te is a sampling period; counting a number of samples obtained for the reflected signal and comparing the number of samples obtained with a number n predefined as a function of a length of the cable or the electrical network to be diagnosed, where n is an integer; repeating the injecting, the sampling, and the counting steps N times, shifting the emission clock signal by a duration ?; reconstituting the reflected signal from n*N samples obtained; and analyzing the reconstituted reflected signal to detect a fault.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 31, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Julien Guilhemsang, Fabrice Auzanneau, Yannick Bonhomme
  • Patent number: 8593187
    Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tyler J. Gomm, Debra Bell