Using Multiple Clocks Patents (Class 327/144)
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Patent number: 11960320Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: April 17, 2023Date of Patent: April 16, 2024Assignee: KIOXIA CORPORATIONInventors: Toshitada Saito, Akihisa Fujimoto
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Patent number: 11934219Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.Type: GrantFiled: March 29, 2022Date of Patent: March 19, 2024Assignee: QUALCOMM INCORPORATEDInventors: Arvind Jain, Divya Gangadharan, Muhammad Nasir, Hong Dai, Madan Krishnappa
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Patent number: 11907005Abstract: A multi-core system includes a multi-core processor, a function block, a clock management circuit, and a control circuit. The multi-core processor includes a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively. The function block communicates with the multi-core processor based on an interface clock signal. The clock management circuit generates each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals. The clock management circuit generates the interface clock signal based on the second clock signal. A control circuit may generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.Type: GrantFiled: December 16, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geunho Choi, Mingoo Kang
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Patent number: 11894848Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.Type: GrantFiled: December 5, 2018Date of Patent: February 6, 2024Assignee: MINIMA PROCESSOR OYInventors: Navneet Gupta, Lauri Koskinen
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Patent number: 11856080Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.Type: GrantFiled: November 29, 2022Date of Patent: December 26, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE 2) SASInventors: Vincent Pascal Onde, Diarmuid Emslie, Patrick Valdenaire
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Patent number: 11831320Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.Type: GrantFiled: February 20, 2023Date of Patent: November 28, 2023Inventors: Swee-Lin Thor, Gim-Eng Chew
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Patent number: 11796592Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: GrantFiled: January 12, 2022Date of Patent: October 24, 2023Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Samuel Paul Visalli
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Patent number: 11733730Abstract: A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.Type: GrantFiled: December 21, 2021Date of Patent: August 22, 2023Assignee: SK hynix Inc.Inventors: Yun Tack Han, Sang Su Lee
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Patent number: 11711509Abstract: A video camera system including: one or more video cameras; a video recorder in communication with each of the one or more video cameras; a video analytics module, the video analytics module being a computer program product embodied on a computer readable medium, the computer program product including instructions that, when executed by a processor, cause the processor to perform operations including: obtaining video parameters of a plurality of video frames received at the video recorder, the plurality of video frames being transmitted from the one or more video cameras to the video recorder; determining an abnormality within the video parameters; and identifying a malfunctioning video camera of the one or more video cameras that produced the abnormality within the video parameters.Type: GrantFiled: March 4, 2020Date of Patent: July 25, 2023Assignee: CARRIER CORPORATIONInventors: Jaroslaw Dobrowolski, Sylwester Mroz
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Patent number: 11695398Abstract: A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.Type: GrantFiled: July 20, 2020Date of Patent: July 4, 2023Inventors: Kai Li, Yuanjun Liang
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Patent number: 11677391Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.Type: GrantFiled: January 26, 2022Date of Patent: June 13, 2023Assignee: Rambus Inc.Inventors: Robert E. Palmer, Andrew M. Fuller, William F. Stonecypher
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Patent number: 11644504Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.Type: GrantFiled: February 14, 2020Date of Patent: May 9, 2023Assignee: STMicroelectronics S.r.l.Inventors: Mirko Dondini, Daniele Mangano, Salvatore Pisasale
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Patent number: 11616503Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.Type: GrantFiled: May 12, 2022Date of Patent: March 28, 2023Assignee: PIXART IMAGING INC.Inventors: Swee-Lin Thor, Gim-Eng Chew
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Patent number: 11601119Abstract: A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.Type: GrantFiled: December 16, 2021Date of Patent: March 7, 2023Assignee: THE BOEING COMPANYInventors: Salim A. Rabaa, Ethan H. Cannon, Manuel F. Cabanas-Holmen
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Patent number: 11579649Abstract: Apparatus and methods for clock duty cycle correction and deskew are provided. In certain embodiments, a clock distribution circuit includes a clock driver that provides a differential clock signal to a clock slicer over a pair of transmission lines. The clock distribution circuit further includes a resistor-inductor-capacitor (RLC) tuning circuit for providing termination between the pair of transmission lines and a differential input to the clock slicer. The RLC tuning circuit includes a pair of resistor digital-to-analog converters (resistor DACs or RDACs) coupled to the pair of transmission lines and a pair of controllable inductor-capacitor (LC) circuits coupled to the pair of transmission lines.Type: GrantFiled: December 30, 2021Date of Patent: February 14, 2023Assignee: Analog Devices, Inc.Inventor: Wei-Hung Chen
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Patent number: 11546073Abstract: A control method and a time aware bridge device for a seamless Precision Time Protocol (PTP) are provided. The control method includes: utilizing the time aware bridge device to pre-configure a first control signal source as a master control signal source, and pre-configure a second control signal source as a backup control signal source; utilizing the time aware bridge device to determine whether one or more packets from the master control signal source conform to at least one predetermined rule to generate a determination result; and selectively configuring the second control signal source as the master control signal source according to the determination result.Type: GrantFiled: May 5, 2021Date of Patent: January 3, 2023Assignee: Realtek Semiconductor Corp.Inventors: Yung-Kun Lin, Chung-Keng Hung, Yan-Liang Wu, Kai-Wen Cheng
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Patent number: 11442521Abstract: A system comprising a plurality of self-powered devices and at least one remote device. The plurality of self-powered devices may be configured to perform instructions. The plurality of self-powered devices may be configured to select one of a plurality of modes of operation. The remote device may be configured to store scheduling data. The remote device may be configured to communicate with the self-powered devices. The self-powered devices may select one of the plurality of modes of operation based on the scheduling data.Type: GrantFiled: October 23, 2019Date of Patent: September 13, 2022Assignee: Invent.ly, LLCInventors: Stephen J. Brown, Daylyn M. Meade, Timothy P. Flood, Clive A. Hallatt, Holden D. Jessup, Hector H. Gonzalez-Banos
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Patent number: 11438200Abstract: A method for communicating between a first radio frequency communications device including a first local oscillator and a second radio frequency communications device including a second local oscillator includes receiving a packet using a receiver of the first radio frequency communications device. The method includes detecting an average frequency offset based on sequential samples of the packet. The method includes applying a first adjustment to the first local oscillator to reduce a frequency offset between the first local oscillator and the second local oscillator. The first adjustment is based on the average frequency offset. The method includes, after adjusting the first local oscillator, transmitting a second packet to the second radio frequency communications device by the first radio frequency communications device using the first adjustment and the first local oscillator.Type: GrantFiled: November 30, 2020Date of Patent: September 6, 2022Assignee: Silicon Laboratories Inc.Inventors: Michael A. Wu, Wentao Li, Yan Zhou
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Patent number: 11371864Abstract: There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.Type: GrantFiled: June 23, 2021Date of Patent: June 28, 2022Assignee: PIXART IMAGING INC.Inventors: Swee-Lin Thor, Gim-Eng Chew
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Patent number: 11256288Abstract: In one aspect, a clock monitor includes a frequency-to-voltage converter (FVC) configured to receive a clock signal and configured to generate a voltage signal in response to the clock signal received. The FVC includes a resistor and a switched capacitor (SC) circuit connected to the resistor to form a resister divider circuit. The switched capacitor circuit includes a capacitor. The clock monitor detects that a clock frequency is zero and/or the clock frequency is not within a frequency range.Type: GrantFiled: February 2, 2021Date of Patent: February 22, 2022Assignee: Allegro MicroSystems, LLCInventors: Matias Fernando Bulacio, Nicolás Ronis, Franco Noel Martin Pirchio
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Patent number: 11251788Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.Type: GrantFiled: July 21, 2017Date of Patent: February 15, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
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Patent number: 11056158Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.Type: GrantFiled: September 16, 2019Date of Patent: July 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Seok Kang, Seungjun Bae
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Patent number: 11039517Abstract: A method for generating fractional PWM pulses to drive an light emitting device includes generating multiphase clock signals using a multiphase PLL or DLL includes the steps of generating a plurality of phases of PWM pulses that correspond to a number of phases of the multiphase clock signals, selecting two or more phases amongst the plurality of PWM pulses, performing logic operations of the selected phases of PWM pulses to generate fractional PWM pulses, and generating a driving current using the fractional PWM pulses in a current source. The light emitting device is can be an LED display comprising an LED array having a plurality of channels and a plurality of scan lines. The driving current drives LEDs in one of the plurality of channels.Type: GrantFiled: June 1, 2020Date of Patent: June 15, 2021Assignee: SCT LTD.Inventors: Eric Li, Shean-Yih Chiou, Shang-Kuan Tang, Juinn-Yan Chen, Yi Zhang, Zhenchao Liu
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Patent number: 11011213Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.Type: GrantFiled: July 22, 2019Date of Patent: May 18, 2021Assignee: LONGITUDE LICENSING LIMITEDInventor: Yoshinori Matsui
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Patent number: 10999050Abstract: A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.Type: GrantFiled: May 4, 2020Date of Patent: May 4, 2021Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventor: Samiksha Agarwal
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Patent number: 10848802Abstract: Embodiments provide techniques for delivering a paced stream of video data packets. One embodiment includes receiving a data stream of video data packets formatted according to a Society of Motion Picture and Television Engineers (SMPTE) standard. A desired rate of delivery for the video data packets at a gateway device is determined. Embodiments generate a padded data stream by inserting one or more pause frames in between the video data packets in the received data stream, based on the desired rate of delivery. The padded data stream is transmitted across a link to a network switch, to be transmitted to the gateway device.Type: GrantFiled: March 9, 2018Date of Patent: November 24, 2020Assignee: Cisco Technology, Inc.Inventors: Andre Surcouf, Mohammed Hawari, Pierre Pfister, Axel Taldir
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Patent number: 10838450Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).Type: GrantFiled: November 2, 2018Date of Patent: November 17, 2020Assignee: Apple Inc.Inventors: Karan Sanghi, Saurabh Garg
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Patent number: 10797683Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.Type: GrantFiled: March 6, 2020Date of Patent: October 6, 2020Assignee: Faraday Technology Corp.Inventors: Vinod Kumar Jain, Chi-Yeu Chao, Prateek Kumar Goyal, Han-Kyul Lim
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Patent number: 10788853Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.Type: GrantFiled: January 31, 2017Date of Patent: September 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Maneesh Soni, Rajeev Suvarna, Nikunj Khare
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Patent number: 10778202Abstract: A clock switching apparatus is provided. The clock input terminal receives a first clock signal as an input clock signal at first and start to receive a second clock signal as the input clock signal during a masking state of a masking signal within a clock-switching time period. The enabling synchronizing circuit receives a clock-switching enabling signal, receives the input clock signal and generate a synchronized enabling signal accordingly. The masking circuit receives the synchronized enabling signal and the mask signal to generate a final enabling signal. The output circuit receives the input clock signal, receive the final enabling signal that disables the output circuit only when either the masking signal is at the masking state or the synchronized enabling signal is at the clock-switching enabling state, and generate an output clock signal according to the input clock signal when the output circuit is enabled.Type: GrantFiled: September 5, 2019Date of Patent: September 15, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Po-Hsien Wu, Li-Yu Chen, Huan-Wen Chen
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Patent number: 10777246Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.Type: GrantFiled: January 31, 2020Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su Yeon Doo, Seungjun Bae, Sihong Kim, Hosung Song
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Patent number: 10712387Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: GrantFiled: March 6, 2019Date of Patent: July 14, 2020Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
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Patent number: 10693589Abstract: Devices and methods are provided for performing a high-frequency jitter self stress check on a receiver to assist with optimization. High-frequency jitter is injected into a clock signal recovered from a received data signal and used to sample the data signal. The injected jitter increases the bit error rate (BER), making BER a more useful and quicker optimization metric in applications using low-noise communication links. Error correction is used to maintain acceptable output BER while the self stress check is in progress.Type: GrantFiled: June 18, 2018Date of Patent: June 23, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Ehud Nir, Henry Wong, Petar Ivanov Krotnev
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Patent number: 10666271Abstract: A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.Type: GrantFiled: July 10, 2019Date of Patent: May 26, 2020Assignee: Beken CorporationInventors: Dawei Guo, Ronghui Kong
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Patent number: 10608646Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.Type: GrantFiled: June 14, 2019Date of Patent: March 31, 2020Assignee: Huawei Technologies Co., Ltd.Inventor: Anders Jakobsson
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Patent number: 10552066Abstract: A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.Type: GrantFiled: August 31, 2017Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventor: Ravi Kiran Kandikonda
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Patent number: 10547317Abstract: A device includes a physical medium attachment (PMA), a physical coding sublayer (PCS), a phase detector, and an oscillator. The PMA receives data at a first speed and overclocks the received data to a second speed, wherein the second speed is higher than the first speed. The PCS receives the data at the second speed. The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions. The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector. The oscillator clocks the PMA based on the adjusted clock.Type: GrantFiled: July 1, 2019Date of Patent: January 28, 2020Assignee: XILINX, INC.Inventors: Paolo Novellini, David F. Taylor, Alastair J. Richardson
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Patent number: 10541693Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: January 8, 2019Date of Patent: January 21, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 10541689Abstract: A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.Type: GrantFiled: July 6, 2018Date of Patent: January 21, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Yu Hsiang Chang, Ching-Hsiang Chang
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Patent number: 10509435Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.Type: GrantFiled: September 29, 2016Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Ramamurthy Krithivas, Mark A. Bordogna, James M. Sepko
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Patent number: 10498314Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.Type: GrantFiled: June 9, 2016Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Steven K. Hsu, Amit Agarwal, Simeon Realov
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Patent number: 10498345Abstract: Various embodiments described herein provide a multiple injection lock ring-based PI that can inject a plurality of clock signals, of different phases, at injection points disposed along the ring chain of the PI and lock phase to those received clock signals (injected clock signals). For instance, an embodiment described herein may provide a multiple injection lock ring-based PI that permits double injection, triple injection, or the like, of clock signals external into the PI.Type: GrantFiled: June 30, 2017Date of Patent: December 3, 2019Assignee: Cadence Design Systems, Inc.Inventors: Sambarta Rakshit, Eric Harris Naviasky
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Patent number: 10474213Abstract: A system comprising a plurality of self-powered devices and at least one remote device. The plurality of self-powered devices may be configured to perform instructions. The plurality of self-powered devices may be configured to select one of a plurality of modes of operation. The remote device may be configured to store scheduling data. The remote device may be configured to communicate with the self-powered devices. The self-powered devices may select one of the plurality of modes of operation based on the scheduling data.Type: GrantFiled: March 16, 2017Date of Patent: November 12, 2019Assignee: Invent.ly, LLCInventors: Stephen J. Brown, Daylyn M. Meade, Timothy P. Flood, Clive A. Hallatt, Holden D. Jessup, Hector H. Gonzalez-Banos
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Patent number: 10379927Abstract: An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.Type: GrantFiled: November 1, 2016Date of Patent: August 13, 2019Assignee: XILINX, INC.Inventors: Lester S. Sanders, Shravanthi Katam, Abhinaya Katta, Jayaram Pvss
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Patent number: 10346240Abstract: A repair information providing device in an integrated circuit including a plurality of memory blocks includes a plurality of faulty cell address registers connected to the memory blocks, respectively, a repair information storage block configured to store repair information including an address of a faulty cell and a memory index indicating a memory block having the faulty cell, a repair information control block configured to read the repair information from the repair information storage block, transfer the address of the faulty cell included in the repair information to the respective faulty cell address registers, and generate a memory block selection signal based on the memory index included in the repair information, and a clock gating block configured to receive a clock signal, and selectively transfer the clock signal to one of the faulty cell address registers connected to the memory block having the faulty cell in response to receiving the memory block selection signal.Type: GrantFiled: April 11, 2016Date of Patent: July 9, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Hee Han, Yo-Seop Lim, Dong-Kwan Han
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Patent number: 10334363Abstract: An audio signal processing circuit is disclosed. The audio signal processing circuit includes a digital signal processing part formed in a digital area, and configured to process a digital audio signal; an analog circuit formed in an analog area, and configured to process an analog audio signal; a frequency divider formed in the digital area, and configured to divide a system clock signal to generate a first clock signal to be provided to the digital signal processing part and a second clock signal to be provided to the analog area; and a retiming circuit formed in the analog area, and configured to retime the second clock signal by using the system clock signal and provide the retimed second clock signal to the analog circuit.Type: GrantFiled: April 4, 2017Date of Patent: June 25, 2019Assignee: ROHM CO., LTD.Inventor: Kinji Ito
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Patent number: 10296488Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.Type: GrantFiled: November 13, 2017Date of Patent: May 21, 2019Assignee: PACT XPP SCHWEIZ AGInventor: Martin Vorbach
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Patent number: 10199086Abstract: An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.Type: GrantFiled: January 29, 2016Date of Patent: February 5, 2019Assignee: Micron Technology, Inc.Inventor: Shingo Tajima
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Patent number: 10193717Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.Type: GrantFiled: January 5, 2018Date of Patent: January 29, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Toshiyuki Yamagishi, Tomoya Horiguchi
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Patent number: 10156608Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.Type: GrantFiled: June 19, 2017Date of Patent: December 18, 2018Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel