Using Multiple Clocks Patents (Class 327/144)
  • Patent number: 10379927
    Abstract: An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: August 13, 2019
    Assignee: XILINX, INC.
    Inventors: Lester S. Sanders, Shravanthi Katam, Abhinaya Katta, Jayaram Pvss
  • Patent number: 10346240
    Abstract: A repair information providing device in an integrated circuit including a plurality of memory blocks includes a plurality of faulty cell address registers connected to the memory blocks, respectively, a repair information storage block configured to store repair information including an address of a faulty cell and a memory index indicating a memory block having the faulty cell, a repair information control block configured to read the repair information from the repair information storage block, transfer the address of the faulty cell included in the repair information to the respective faulty cell address registers, and generate a memory block selection signal based on the memory index included in the repair information, and a clock gating block configured to receive a clock signal, and selectively transfer the clock signal to one of the faulty cell address registers connected to the memory block having the faulty cell in response to receiving the memory block selection signal.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Hee Han, Yo-Seop Lim, Dong-Kwan Han
  • Patent number: 10334363
    Abstract: An audio signal processing circuit is disclosed. The audio signal processing circuit includes a digital signal processing part formed in a digital area, and configured to process a digital audio signal; an analog circuit formed in an analog area, and configured to process an analog audio signal; a frequency divider formed in the digital area, and configured to divide a system clock signal to generate a first clock signal to be provided to the digital signal processing part and a second clock signal to be provided to the analog area; and a retiming circuit formed in the analog area, and configured to retime the second clock signal by using the system clock signal and provide the retimed second clock signal to the analog circuit.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 25, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Kinji Ito
  • Patent number: 10296488
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 21, 2019
    Assignee: PACT XPP SCHWEIZ AG
    Inventor: Martin Vorbach
  • Patent number: 10199086
    Abstract: An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shingo Tajima
  • Patent number: 10193717
    Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 29, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiyuki Yamagishi, Tomoya Horiguchi
  • Patent number: 10159053
    Abstract: Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Joaquin Romera, Graig Zethner, Raheel Khan
  • Patent number: 10156608
    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 18, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10082540
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10079639
    Abstract: A test and measurement instrument includes a first input port and a second input port that receive a first input signal modulated according to a first clock signal and a second input signal modulated according to a second clock signal, respectively. The first clock signal and the second clock signal may be asynchronous. The instrument also includes a phase reference that generates clock data for the second clock signal. The instrument includes a processor that determines time bases for the input signals that comprise different rates based on the received and/or generated clock data. The instrument also includes a display coupled to the processor. The display concurrently displays the first input signal in a first graticule according to the first time base and the second input signal in a second graticule according to the second time base.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 18, 2018
    Assignee: Tektronix, Inc.
    Inventor: Jan P. Peeters Weem
  • Patent number: 10054639
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 21, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10056989
    Abstract: Methods and various structures provide for loopback tuning, testing, and calibrating of a transceiver, including: supplying RF drive to both a transmitter and a receiver of the transceiver from one oscillator; applying a modulation waveform to a transceiver block of the transceiver to produce an amplitude-modulated signal; converting a sideband of the amplitude-modulated signal to a baseband signal having a frequency suitable for processing by a receiver digital block, where processing the baseband signal produces a digital output; and performing tuning, testing, and calibrating of the transceiver block, based at least in part on the digital output.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 21, 2018
    Assignee: Arm Limited
    Inventors: Anthony Kresimir Stampalia, Mario Lafuente
  • Patent number: 10033520
    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 24, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J (Nick) Huang, Delong Cui, Afshin Momtaz
  • Patent number: 9948321
    Abstract: A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: April 17, 2018
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Jeong Kyoum Kim
  • Patent number: 9912323
    Abstract: The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: March 6, 2018
    Assignee: MICRO RESEARCH & DEVELOPMENT CORPORATION
    Inventor: Sasan Ardalan
  • Patent number: 9797948
    Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Milan Shetty, Srinivasulu Alampally, Prasanth V
  • Patent number: 9794007
    Abstract: Methods and various structures provide for loopback tuning, testing, and calibrating of a transceiver, including: supplying RF drive to both a transmitter and a receiver of the transceiver from one oscillator; applying a modulation waveform to a transceiver block of the transceiver to produce an amplitude-modulated signal; converting a sideband of the amplitude-modulated signal to a baseband signal having a frequency suitable for processing by a receiver digital block, where processing the baseband signal produces a digital output; and performing tuning, testing, and calibrating of the transceiver block, based at least in part on the digital output.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 17, 2017
    Assignee: ARM Limited
    Inventors: Anthony Kresimir Stampalia, Mario Lafuente
  • Patent number: 9733308
    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 15, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9716506
    Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.
    Type: Grant
    Filed: September 10, 2016
    Date of Patent: July 25, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Yung Chen, Yu-Chiang Liao
  • Patent number: 9698808
    Abstract: A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 4, 2017
    Assignee: Cavium, Inc.
    Inventors: Scott E. Meninger, Lu Wang
  • Patent number: 9671819
    Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 6, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Pirozzi
  • Patent number: 9674032
    Abstract: A real-time distributed network module arranged to provide an interface between at least one master application and at least one real-time distributed network. The real-time distributed network module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection at least one master application interface component arranged to provide an interface to the at least one master application, and at least one configuration component arranged to perform mapping of communication channels between the first communications component, the at least one further communications component and the at least one master application interface component.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Graham Edmiston, Hezi Rahamim
  • Patent number: 9621333
    Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: George Alan Wiley, Ohjoon Kwon
  • Patent number: 9595972
    Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: March 14, 2017
    Assignee: Microsemi Semiconductor ULC
    Inventors: Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Paul H. L. M. Schram, Mark A Warriner
  • Patent number: 9503978
    Abstract: Timing resolution for user equipments (UEs) that operate using a discontinuous reception (DRX) mode that includes various sleep cycles may be addressed through selection of various alternative wake up procedures. A UE selects a wake-up procedure based on the length of the sleep cycle. The UE may use details of the sleep cycle, including a time offset or timing uncertainty associated with the sleep cycle, when selecting the wake-up procedure. The UE may select to obtain system timing information either directly from a serving cell or non-serving cell in sync with the serving cell or may select to perform either a one-step or two-step pre-wake up procedure in order to obtain the system timing. Once the UE obtains the system timing or determines a wake-up procedure, it performs timing correction before the scheduled wake-up times between the sleep cycles.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Tingfang Ji, Brian Clarke Banister, Peter Gaal, Hao Xu
  • Patent number: 9471087
    Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Huy T. Vo, Yantao Ma
  • Patent number: 9420332
    Abstract: This disclosure describes audio decoding techniques for decoding audio information that needs to be properly clocked. In accordance with this disclosure, the number of audio samples in decoded audio output can be adjusted to compensate for an estimated error the in decoder clock. That is to say, rather than adjust the decoder clock to synchronize the decoder clock to the encoder clock, this disclosure proposes adding or removing audio samples from the decoded audio output in order to ensure that the decoded audio output is properly timed. In this way, the techniques of this disclosure can eliminate the need for an adjustable or controllable clock at the decoding device, which can save cost and/or allow legacy devices that do not include an adjustable or controllable clock to decode and output audio information that needs to be properly clocked.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: August 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Nischal Abrol, Sivaramakrishna Veerepalli, Stephen Verrall, Sandeep Singhai
  • Patent number: 9203415
    Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: December 1, 2015
    Assignee: ST-ERICSSON SA
    Inventors: David Jacquet, Philip O'Shea, Jacques Prunier
  • Patent number: 9129694
    Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Daesik Song
  • Patent number: 9042404
    Abstract: The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventors: Keith Duwel, Michael Menghui Zheng, Vinson Chan, Kalyan Kankipati
  • Publication number: 20150123720
    Abstract: Embodiments of quantum clocks for a master/slave architecture are generally described herein. In some embodiments, a coupled pair of entangled particles is generated using a particle source. A first of the entangled particles of the coupled pair is used as a master clock. A second of the entangled particles of the coupled pair is used as a slave clock. Quantum states of the first entangled particle of the coupled pair associated with the master clock and the second of the entangled particles of the coupled pair associated with the slave clock are entangled by an Einstein-Podolsky-Rosen (EPR) link.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Raytheon Company
    Inventors: Steven J. Silverman, Nils Paz, John R. Harmon
  • Patent number: 9018990
    Abstract: A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 28, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ye Liu
  • Patent number: 9000815
    Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
  • Patent number: 8994419
    Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young-Jun Ku
  • Patent number: 8981854
    Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8976054
    Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
  • Patent number: 8971143
    Abstract: Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.a.r.l
    Inventors: Takuyo Kodama, Kosuke Goto
  • Patent number: 8952836
    Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: February 10, 2015
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Hongwei Zhu, Yuwei Zhao
  • Patent number: 8928374
    Abstract: To realize an optimal power-on reset in a system in which the rise of the power supply voltage is sharp. A semiconductor device according to the present invention includes two diodes connected in parallel between power supplies, and a resistor circuit and a capacitance element connected in parallel between one power supply and each of the two diodes, and outputs a comparison result between voltages outputted from the two resistor circuits as a reset signal.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 8922263
    Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Kamizuma, Taizo Yamawaki, Yukinori Akamine, Koji Maeda
  • Patent number: 8917123
    Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Swapnil Bahl, Shray Khullar
  • Patent number: 8902007
    Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8867681
    Abstract: A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first calculation circuit which calculates a first difference value indicating a frequency difference value between a common clock supplied from the control device and a first clock as a clock used in the first transmission device; and a transmitter which reports the first difference value to a second transmission device other than the first transmission device, wherein the second transmission device comprises: a second calculation circuit which calculates a second difference value indicating a frequency difference value between the common clock and a second clock used in the second transmission device, and a frequency controller which controls an oscillator generating the second clock so that the second difference value approaches the first difference value reported from the first transmission device.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Yoshida
  • Patent number: 8867684
    Abstract: An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 21, 2014
    Assignee: Dialog Semiconductor GmbH
    Inventor: Nir Dahan
  • Publication number: 20140292385
    Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics International N.V.
    Inventors: SWAPNIL BAHL, Shray Khullar
  • Publication number: 20140281652
    Abstract: A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Tukaram Shankar Methar, Nilesh Acharya, Jyotirmaya Swain, Brian Lawrence Smith
  • Patent number: 8816776
    Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Vladimir Sindalovsky, Mohammad S. Mobin, Lane A. Smith
  • Patent number: 8806066
    Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Schuman Assets Bros. LLC
    Inventor: Stephen Waller Melvin
  • Publication number: 20140210524
    Abstract: Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a remote signal transmitted by an external device. The received signal is provided to a clocking circuit having a clocking circuit for computation of a calibration factor based on a difference between phases of the clock signal generated by the local clock and transitions in the received remote signal. The calibration factor may be derived as a function of an edge of the clock signal lagging or leading relative to a corresponding edge of the remote signal.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 31, 2014
    Applicant: MEDTRONIC, INC.
    Inventor: Melvin P. Roberts
  • Publication number: 20140203850
    Abstract: Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal. The clock gater is configured to provide the input clock to the plurality of synchronizers only upon receiving the enable signal. The circuitry also includes an enable generator coupled to receive the asynchronous input signals and configured to generate the enable signal for the clock gater responsive to the asynchronous input signals.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Applicant: APPLE INC.
    Inventors: Gilbert Herbeck, Erik Machnicki