Abstract: A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: An input signal is received having a period and an input pulse width. The input pulse width of an input signal is adjusted to an output pulse width of an output signal based upon a recording control signal for control of recording on a storage medium. The output signal and the output pulse width is derived from a triggering edge of a first selected signal of a first selected phase and a triggering edge of a second selected signal of a second selected phase in succession. The first selected signal and the second selected signal are selected from an assortment of reference signals that have distinct relative phases to provide the output pulse width of a desired duration. The number of distinct relative phases available for formation of the output pulse width is increased by one or more of the following: delaying, dividing, inverting, and interpolating one or more reference signals.

Abstract: A circuit for providing a minimum wake-up time, in which a monostable circuit generates the WAKE-UP signal for a time at least as long as a minimum time established by the monostable circuit. The circuit is structured to extend the WAKE-UP signal for a time necessary to equal the minimum time that is established by the monostable circuit and to disable the WAKE-UP signal at the end of the variation of the input signal of the device being controlled.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor stage in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.

Abstract: First and second pulse train generating units each generates first and second pulse trains each having a positive polarity and a negative polarity corresponding to one and other polarity elements among positive and negative polarity elements which configure the electric signal in the sine waveform outputted from a signal generating unit. A phase difference setting unit sets the phase difference between the first and second pulse trains so that a pulse of the first and second pulse trains which are generated by the first and second pulse train generating units are partially superimposed temporally. A wave synthesizing unit synthesizes the first and second pulse trains, in which the phase difference. A half-wave rectifying unit half-wave rectifies the output from the wave synthesizing unit and generates a pulse train having a pulse width narrower than any of the pulse widths owned by the first and second pulse trains.

Abstract: An output circuit generates an output signal. The output signal has a duty cycle from an input signal. A level extractor couple to the output circuit to extract a direct current (DC) level from the output signal. The DC level is a representative of the duty cycle. An integrator couple to the level extractor to integrate the DC level. The integrator generates a current control signal to adjust the duty cycle.

Abstract: A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.

Abstract: An electronic circuit generates additional clock edges from a reference clock signal utilizing switch-capacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.

Abstract: A circuit for providing a pulsed signal to a driven device such as a tattoo imprinting machine wherein the pulse width and signal magnitude and frequency are controlled by the operator. A voltage controlled oscillator establishes the signal frequency, a variable impedance provides operator control of the signal magnitude and a foot-actuated switch enables the operator to control pulse width for intermittent operation. An adjustable frequency controller enables the operator to control the oscillator.

Abstract: A method and an electrical circuit for converting highly structured analog signals arriving with variable pulse frequency into trigger pulses with an electronic circuit that locks the trigger pulses for a specific time, which is referred to as a dead time. The dead time being adapted to the current pulse frequency of the analog signals.

Abstract: When a sub-clock signal is generated in synchronization with an external main clock signal from the main clock signal and its inverted delay signal, the signal width of the sub-clock signal is constant even when the high level or the low level of the main clock signal is shorter than the inverted delay time. A holding 20 circuit is provided so that a high level time period of the system clock signal CLK1 is extended beyond the delay time of the delay circuit 30. A complex gate including OR gates 25 and 27 is provided in a delay gate chain of a non-inversion in the holding circuit. If the high level width of the main clock signal CLK1 is not less than a time corresponding to four stages of the NAND gates 21 to 22, it is possible to extend the high level width of the gate chain output signal S28 to a time corresponding to twelve stages. A complex gate including NAND gates 31 and 32 is provided in the gate chain of the delay circuit 30 for the inversion and delay.

Abstract: A pulse generating apparatus efficiently generates a pulse signal by receiving a control signal. A voltage level controller 20 receives a control signal and outputs a certain voltage through a node N0. A output level variation element C is placed between a node N0 and a node N1. A switching element 30 applies a high voltage Vcc to the node N1. A switching element 40 applies a low voltage Vss to the node N1. The pulse is generated by a logic operation of the control signal and a voltage on a node N0.

Abstract: An apparatus is provided for processing a pulse signal. The apparatus includes (1) a pulse-shrinking circuit for shrinking a specific quantity of a pulse width of the pulse signal; and (2) a feedback circuit electrically connected to the pulse-shrinking circuit for repetitively feeding the output pulse signal back to the input end of the pulse-shrinking circuit, the shrunk output pulse signal being further shrunk by the pulse-shrinking circuit in order to obtain a feedback number of the pulse signal before the pulse signal is vanished.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: An asynchronous flag generator for generating an asynchronous flag having a minimum defined active pulse length. The asynchronous flag generator comprises an arbitrary length flag generator for generating an arbitrary length status flag signal from at least two asynchronous signals, one being a set flag signal and the other being a clear flag signal. A minimum pulse generator for generating a minimum pulse having a predefined pulse length upon initiation of the set flag signal. Combinational logic combines the arbitrary length status flag with the minimum pulse to generate an asynchronous status flag with a defined minimum active pulse length.

Abstract: Feedback pulse generators each have an input and an output, a first digital gating circuit, and a second digital gating circuit. The first digital gating circuit is coupled between the input and the output of the pulse generator, and is responsive to an input signal from an external source changing from a first logic state to a second logic state that is received at a first input thereof for initiating a pulse at the output of the pulse generator.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A pulse-width controller for a switching regulator is provided. The pulse-width controller is coupled to a bulk regulator in the switching regulator to control the bulk regulator to produce an output voltage in a fixed level and an output current in a desired level in response to various demands from the load. The pulse-width controller takes a voltage of feedback-voltage indicative of a change in the output voltage of the bulk regulator and a first voltage of feedback-current and a second voltage of feedback-current indicative of a change in the output current of the bulk regulator as feedback signals. These feedback signals can cause the pulse-width controller to produce a square-wave signal with an adaptive pulse width that controls the bulk regulator to produce the output voltage and current in the desired levels.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.

Abstract: A dynamic/static signal converting circuit and method for use in a lamp driving device has a clock delay unit for delaying a system clock signal for a predetermined period of time; a converting unit for receiving a dynamic signal for driving an LED, synchronizing the dynamic signal with a delayed system clock signal and then converting the dynamic signal into a static signal; and an LED driving unit for driving the LED in response to the static signal output from the converting unit.

Abstract: A circuit for detecting contact of a magneto-resistive (MR) head with a disk surface by properly sensing disturbance signals without being effected by noises using a simple configuration. The circuit for detecting contact of the MR head with the disk surface by sensing a disturbance waveform generated by MR head contact with the disk surface comprises a comparator for comparing a signal read out by MR head with a threshold level V.sub.th ; a pulse width limiting circuit for restricting a pulse width x, which is wider than the predetermined pulse width x.sub.1, to a pulse width x.sub.1 ; and a D flip-flop circuit in which an output signal of the comparator being applied to both D terminal and R terminal, and an output signal from the pulse width limiting circuit being applied to T terminal, and an output signal being obtained from an inverted output terminal QC.

Abstract: An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment.

Abstract: A dead-time generating circuit includes a first gate for generating a gate signal corresponding to a predetermined cutting width, and a second gate for cutting an input signal to be cut by the gate signal by the predetermined cutting width determined by a user and outputting the result. Therefore, an arbitrary block of a pulse width modulated (PWM) signal (whatever it may be in a logic "high" or "low") applied to the inverter of an AC servo driving circuit can be cut constantly by a predetermined cutting width. Also, the cutting width can be adjusted easily by the user.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Abstract: A apparatus for generating an output signal of a desired pulse width is disclosed. The apparatus comprises a flip-flop, a delay circuit and a clear circuit. The flip-flop, in response to a first trigger signal, outputs the output signal at an output terminal. The delay circuit generates a second trigger signal by delaying the output signal for a predetermined amount of time. The clear circuit, in response to the second trigger signal, generates a clear signal to said flip-flop in order to clear the output signal. The desired pulse width of the output signal is controlled by the predetermined amount of time set in the delay circuit.

Abstract: In a circuit arrangement having a switching amplifier (10), particularly for hearing aids, for limiting a pulse-width-modulated signal (S3) that is formed for a low-frequency signal (S1) and a higher-frequency delta signal (S2), a limitation of the output signal from the switching amplifier is achieved without a reduction in gain given only slight distortions. To that end, the pulse-width-modulated signal (S3) is supplied to a circuit (5; 14; 18) which modifies the width (D1, D2, D4) of individual pulses in the pulse-width-modulated signal (S3), whose width (D1, D2, D4) is longer or/and shorter than a maximum or minimum pulse width D3; D5) prescribable by the circuit (5; 14; 18). The pulse-width-modulated signal (S5; S6) modified by the circuit (5; 14; 18) can be supplied to the switching amplifier (10) as an input signal.