Duty Cycle Control Patents (Class 327/175)
  • Patent number: 11329641
    Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Tai Sik Shin, Dong Shin Jo
  • Patent number: 11294419
    Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 11290096
    Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Tsung-Hsien Tsai
  • Patent number: 11276444
    Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Tai Sik Shin, Dong Shin Jo
  • Patent number: 11276280
    Abstract: An in-vehicle apparatus includes a first pulse generator configured to generate a first pulse in accordance with predetermined equipment before a data stream transmitted from the equipment is received; a second pulse generator configured to generate a second pulse based on the received data stream; an output device configured to output a warning sound based on the first pulse or the second pulse; and a switching device configured to output the first pulse to the output device before the data stream is received, and output the second pulse to the output device as of when the first pulse and the second pulse coincide.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 15, 2022
    Assignee: ALPINE ELECTRONICS, INC.
    Inventor: Osamu Shinohara
  • Patent number: 11264979
    Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Mao-Ruei Li, Ming Hsien Tsai, Ruey-Bin Sheen
  • Patent number: 11257531
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 11218141
    Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 4, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi
  • Patent number: 11159152
    Abstract: Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: October 26, 2021
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Chandrashekhar Reddy Ayya, Srishti Garg
  • Patent number: 11100967
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 11088681
    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11062781
    Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Zhen-Hong Hung, Shih-Yang Sun, Sheng-Wen Chen
  • Patent number: 11012061
    Abstract: A circuit includes a core circuit configured to receive an input clock and output and output clock in accordance with a control signal, the core circuit having an encoder configured to encode the control signal into a plurality of control words and a plurality of duty cycle correction buffers configured in a cascade topology and controlled by said plurality of control words, respectively; a duty cycle detection circuit configured to output a logical signal in accordance with a comparison of a duty cycle of the output clock with a target value; and a controller configured to output the control signal in accordance with the logical signal.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11005468
    Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 11, 2021
    Assignee: Faraday Technology Corp.
    Inventors: Sivaramakrishnan Subramanian, Sridhar Cheruku, Sandeep Kumar Mohanta, Hussainvali Shaik
  • Patent number: 10998888
    Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongho Shin, Kyungtae Kang, Junha Lee, Tongsung Kim, Jangwoo Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 10983443
    Abstract: A control device actuates actuator unit to set a position of an optical element of a lithography system. The control device includes an amplifier unit for providing a control signal for the actuator unit via a voltage signal and a PWM signal. The PWM signal has a duty factor and a clock frequency. The control device also includes a modulator unit designed to provide the PWM signal having the duty factor and a defined clock frequency from a plurality of defined clock frequencies. A defined clock frequency of the plurality of defined clock frequencies is an integer multiple of a basic clock frequency. The basic clock frequency is in the range of 10 kHz to 1 MHz.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Stefan Krone, Lars Berger, Ralf Kiesel, Paul Wijlaars
  • Patent number: 10972078
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam
  • Patent number: 10957367
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10958257
    Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Tsung-Hsien Tsai
  • Patent number: 10951198
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a clock supply circuit, a first output circuit, and a second output circuit. The clock supply circuit outputs a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period. The m is a natural number of 2 or more. The first output circuit outputs a first signal indicating content of data to an outside when a first operation is performed and outputs a second signal having a toggle pattern based on the first clock to the outside when a second operation is performed. The second output circuit outputs an operation clock based on the first clock to the outside when the first operation is performed and outputs a sampling clock based on the second clock to the outside when the second operation is performed.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 16, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroaki Iijima
  • Patent number: 10944386
    Abstract: Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Wu, Ying Duan, Zhi Zhu
  • Patent number: 10923175
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Patent number: 10833656
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Qiang Tang
  • Patent number: 10826391
    Abstract: A power supply for a smooth power output level transitioning includes an energy storage circuit for temporarily storing electric energy for driving a load, a semiconductor switch for pulse-width modulation (PWM) switching, and a digital PWM controller. The digital PWM controller generates a driving waveform to regulate on and off status of the semiconductor switch. The driving waveform toggles between PWM periods of a first type and PWM periods of a second type, and gradually adjusts a ratio of numbers of the PWM periods of the two types over time. The toggling driving waveform achieves one or more intermediate finer power output level that cannot be realized by a single type of PWM period with an intermediate duty cycle, due to the minimum item unit of the driving waveform limited by a clock rate of the digital PWM controller.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 3, 2020
    Assignee: LICON TECHNOLOGY CORPORATION
    Inventors: William Reed, Andrew Davis, Matthew Whitlock, Brent Dae Hermsmeier
  • Patent number: 10826476
    Abstract: Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Barry L. Stakely
  • Patent number: 10819322
    Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 27, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: An-Ming Lee, Chia-Liang Lin, Yo-Hao Tu, Yu-Hsiang Chen
  • Patent number: 10802447
    Abstract: The present disclosure relates to a circuit and method of operation thereof for linearized time amplifier architecture for sub-picosecond resolution. More particularly, the disclosure is directed to an asymmetric edge manipulator whose output is fed to four series of transistors and is operatively coupled to a reset. The disclosure relates to outputting a pair of signals that correspond to a first input and second input of a known and measured clock that may be adjustable with gain to be perceptible to an external device that can then correct for the gain to allow measurement of sub-picosecond resolution.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Kevin Grout
  • Patent number: 10784846
    Abstract: Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Barry L. Stakely
  • Patent number: 10784847
    Abstract: A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 22, 2020
    Assignee: NXP B.V.
    Inventors: Prakhar Tandon, Shivesh Kumar Dubey
  • Patent number: 10756717
    Abstract: A system and method for calibrating a pulse width modulation (PWM) signal that extends the on time by a higher resolution increment. The system comprises a PWM generator that receives a VDDIO rail to generate first and second PWM signals, the second PWM signal having an on time extended by the higher resolution increment having a commanded length. The system further comprises a VDDIO circuit that receives the VDDIO rail and outputs a VDDIO signal. First and second analog-to-digital converters are configured to generate a first and second sets of PWM samples and first and second sets of VDDIO samples. A microcontroller is configured to calculate an actual increment length based on the samples, and to compensate for a difference between the commanded length and the actual increment length.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Eric Patrick Best
  • Patent number: 10749538
    Abstract: An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Marco Bucci, Raimondo Luzzi
  • Patent number: 10727816
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam
  • Patent number: 10715127
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 10673328
    Abstract: An amount of charge transferred by a power converter is estimated by developing a signal that is a combination of signals representing an output voltage of a power converter and an inductor current of the power converter, charging a capacitor with a current proportional to that signal and comparing a voltage developed across the capacitor due to that charging to develop a signal for initiating a pulse to control input of power from a voltage source to the power converter. By using a signal developed in this way, response to both step-up and step-down transients can be improved and, in multi-phase embodiments, ripple cancellation problems such as noise susceptibility and loss of pulse generation can be entirely avoided.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 2, 2020
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Syed Bari, Fred C. Lee, Qiang Li
  • Patent number: 10666234
    Abstract: A transmission circuit includes: a data generating circuit configured to generate data based on a clock signal; a clock generating circuit configured to supply the clock signal to the data generating circuit; and a duty ratio controlling circuit configured to detect a duty cycle distortion of the data output from the data generating circuit, and control a duty ratio of the clock signal based on a result of the detection.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 26, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Daisuke Suzuki, Shigeaki Kawai
  • Patent number: 10641697
    Abstract: A device for counting particles comprises a detector arranged to produce an electrical measurement signal in response to the passage of one or more particles, and a comparator arranged to compare the measurement signal with a threshold signal and to increment a counting value when the measurement signal exceeds the threshold signal, characterized in that it furthermore comprises a threshold-adjusting circuit that applies a lowpass filter to the measurement signal, and that is connected to the comparator in order to use the resulting signal as threshold signal.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 5, 2020
    Assignee: HORIBA ABX SAS
    Inventor: Guilhem Couderc
  • Patent number: 10644680
    Abstract: Systems, apparatuses, and methods for applying duty cycle correction to a level shifter via a feedback common mode resistor are disclosed. A circuit includes a capacitor, an inverter, and at least one feedback resistor. An input signal is received and coupled through the capacitor to the inverter. To correct for duty cycle distortion on the input signal, a duty cycle correction signal is applied to the at least one feedback resistor in the feedback path. The duty cycle correction signal can be applied as a voltage or as a current. In one implementation, the location of the injection point for applying the duty cycle correction signal within the at least one feedback resistor is programmable.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 5, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Tracy J. Feist
  • Patent number: 10630272
    Abstract: Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 21, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Milad Ataei Ashtiani, Kiarash Gharibdoust
  • Patent number: 10608616
    Abstract: Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: March 31, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Charles Joseph Dedic
  • Patent number: 10599481
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Apple Inc.
    Inventors: Constantin Pistol, Daniel A. Chimene, Jeremy C. Andrus, Russell A. Blaine, Kushal Dalmia
  • Patent number: 10587247
    Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: March 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tianyu Tang, Venkatesh Ramachandra, Srinivas Rajendra
  • Patent number: 10547298
    Abstract: The present disclosure relates to an apparatus and method for correcting a duty cycle of at least one signal. The apparatus may comprise at least one set of inverters configured to receive the at least one signal and correct the duty cycle of the at least one signal at a correction location of a plurality of correction locations based upon, at least in part, a transmission rate mode of a plurality of transmission rate modes.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rania Hassan Abdellatif Abdelrahim Mekky, Guillaume Fortin, Michael Ben Venditti
  • Patent number: 10530350
    Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: January 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi
  • Patent number: 10529398
    Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 10530349
    Abstract: In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 7, 2020
    Assignee: DENSO CORPORATION
    Inventor: Akifumi Araragi
  • Patent number: 10511313
    Abstract: A phase-detecting method for testing an under-test circuit under control of a testing station includes the steps of receiving input and output signals of the under-test circuit, combining the input and output signals with each other and accordingly generating a frequency-doubled signal, comparing the frequency-doubled signal with a reference clock signal at a same clock rate and accordingly generating a difference signal, filtering the difference signal and accordingly generating a filtered signal, and determining whether the filtered signal is in an acceptable range and accordingly report a result to the testing station.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 17, 2019
    Assignees: Goke Taiwan Research Laboratory Ltd., Xinsheng Intelligent Technology Co., Ltd.
    Inventors: Po-Chien Chang, Jung-Chi Wang
  • Patent number: 10505457
    Abstract: A dimmer is provided for controlling power to a load, the dimmer having a ground leakage power supply deriving power from a connection of the dimmer to ground. The power supply may be a switching-mode power supply that can be the sole or primary power supply to power operation of the dimmer, including operation of the controller.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 10, 2019
    Assignee: LEVITON MANUFACTURING CO., INC.
    Inventors: Levan Papismedov, Alfred Lombardi, Michael Ostrovsky, Ozgur Keser
  • Patent number: 10505450
    Abstract: A servo block in a Buck, Boost, or switching converter allows a positive offset to be applied to the DAC voltage. In a typical switching converter application, the load will have a positive current, sourced from the switching converter to ground through the load. This will cause the output voltage of the switching converter to fall with the output impedance. The servo block corrects the output voltage by adjusting the DAC voltage upwards. In the case where current is forced back into the switching converter, causing the output voltage to rise, the servo block will have affect. The behavior of the servo block is desirable as it reduces the negative affect the servo block may have on load transients occurring when the switching converter is in over voltage. In particular, the idea of shifting the DAC voltage for several different loops with a single servo block is disclosed.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mark Childs, Pietro Gallina, Vincenzo Bisogno
  • Patent number: 10437472
    Abstract: A storage system and method for dynamic duty cycle correction are disclosed. In one embodiment, a controller of a storage system provides a clock signal to the memory, receives the clock signal back from the memory, monitors the duty cycle of the clock signal received back from the memory, and in response to the duty cycle of the clock signal received back from the memory not meeting a target value, adjusts the duty cycle of the clock signal provided to the memory so that the duty cycle of the clock signal received back from the memory better meets the target value. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 8, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ekram Bhuiyan, Steve Chi
  • Patent number: 10411675
    Abstract: In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 10, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Jaewook Kim, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong