Duty Cycle Control Patents (Class 327/175)
  • Patent number: 11921651
    Abstract: An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 5, 2024
    Assignee: AyDeeKay LLC
    Inventors: Mohammad Radfar, Scott David Kee, Jeffrey Michael Zachan, Craig Petku
  • Patent number: 11916554
    Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali
  • Patent number: 11894102
    Abstract: A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventors: Chang Kwon Lee, Su Hyun Oh, Jin Hyung Lee
  • Patent number: 11888481
    Abstract: An apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 30, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Dong-Young Chang, Steven Ernest Finn
  • Patent number: 11881860
    Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 23, 2024
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Shin-Hyun Jeong, Yongun Jeong, Suhwan Kim
  • Patent number: 11869619
    Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 9, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Prasad Ramachandra
  • Patent number: 11831751
    Abstract: A computer-implemented method of generating a one-time pad for use in encryption, the method comprising: determining a seed sequence and an ordered set of initial values; and for each initial value, computing a sequence of terms, wherein each term of the sequence is computed by combining at least one other term of that sequence with at least one term of a previous one of the sequences using modular arithmetic, the previous sequence being the sequence generated for the previous initial value or, in the case of the first initial value, the seed sequence. Rather than using the final sequence as a direct basis for the one-time pad, one or more additional steps are taken to disrupt the final sequence, in order to improve the security of the method and the resulting one-time pad.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: November 28, 2023
    Assignee: REAMC Limited
    Inventor: Roy Silva Wikramaratna
  • Patent number: 11824545
    Abstract: A duty point detection circuit receiving an input signal and generating an output signal includes a charge pump receiving the input signal and the output signal and generating a comparison target signal from the input signal and the output signal, a magnitude of the comparison target signal being determined based on a first duty ratio of the input signal and a second duty ratio of the output signal, a comparator receiving a reference signal and the comparison target signal, and comparing the reference signal and the comparison target signal to generate a comparison result signal, and a control circuit receiving the input signal and the comparison result signal and adjusting the second duty ratio of the output signal to a constant duty ratio in successive cycle periods of the input signal.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunseok Nam
  • Patent number: 11808891
    Abstract: Methods and systems for performing three dimensional LIDAR measurements with an integrated LIDAR measurement device are described herein. In one aspect, a Gallium Nitride (GaN) based illumination driver integrated circuit (IC), an illumination source, and a return signal receiver IC are mounted to a common substrate. The illumination driver IC provides a pulse of electrical power to the illumination source in response to a pulse trigger signal received from the return signal receiver IC. In another aspect, the GaN based illumination driver IC controls the amplitude, ramp rate, and duration of the pulse of electrical power based on command signals communicated from the return signal receiver IC to the illumination driver IC. In a further aspect, illumination driver IC reduces the amount of electrical power consumed by the illumination driver IC during periods of time when the illumination driver IC is not providing electrical power to the illumination source.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 7, 2023
    Assignee: Velodyne Lidar USA, Inc.
    Inventors: David S. Hall, Raymond Liou, Oren Milgrome, Marius Paul Dumitrean
  • Patent number: 11804828
    Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jieming Qi, Daniel Mark Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie Ellen Cox, Timothy O. Dickson
  • Patent number: 11791805
    Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 17, 2023
    Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
  • Patent number: 11777474
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Patent number: 11764771
    Abstract: An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: September 19, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Chieh Wang
  • Patent number: 11762413
    Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Suresh Balasubramanian, Sunil Bhosekar, Bruce Andrew Doyle, Chad O. Lackey, Sharath R. Srinivasan, Erick O. Torres, Khaled M. Alashmouny
  • Patent number: 11757432
    Abstract: A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 12, 2023
    Assignee: AP Memory Technology (Hangzhou) Limited Co
    Inventors: Xuan Zhang, Po Han Chen, Keng Lone Wong, Alessandro Minzoni
  • Patent number: 11742016
    Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hojun Yoon, Wonjoo Jung, Jaewoo Park, Youngchul Cho, Youngdon Choi, Junghwan Choi
  • Patent number: 11722128
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Patent number: 11671086
    Abstract: A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: June 6, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuya Kimura, Hisashi Owa, Takashi Nakamura
  • Patent number: 11662762
    Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 11658644
    Abstract: A method and system for controlling duty cycle distortion in a signal. The system includes an input configured to receive a square wave input signal and a filter configured to transform the square wave input signal into a signal with sloped transitions. One or more linear buffers introduce duty cycle distortion into the signal based on a duty cycle distortion signal to create a duty cycle distorted signal. One or more output buffers receive and transform the duty cycle distorted signal into a distorted square wave signal. A feedback loop receives the distorted square wave signal and compares it to a duty cycle distortion control signal to generate an error signal, which indicates the difference between the square wave signal and the desired output duty cycle. The error signal is converted to the duty cycle distortion signal and presented to the one or more linear buffers.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 23, 2023
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Dario Soltesz, Quazi Ikram, Saman Jafarlou
  • Patent number: 11614789
    Abstract: A system and method for docking a processing unit provided. According to the method, the system dithers between the two signals provided by the two clock generators so as to clock the processing unit at an average clock frequency having a value between the frequencies of the two signals. The average clock frequency is adjusted by modifying the proportion of time spent on one clock signal vs the other clock signal.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 28, 2023
    Assignee: GRAPHCORE LIMITED
    Inventor: Ian Malcolm King
  • Patent number: 11611335
    Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei Shuo Lin
  • Patent number: 11552546
    Abstract: The present invention discloses a multi-phase power supply dynamic response control circuit and a control method. When a rapid rise of the load is detected, an output PWM signal is temporarily adjusted to enter a second operation mode from a first operation mode to supplement energy to the load and prevent the output voltage from decreasing. The present invention requires little modification to the existing circuit, and adopts simple, explicit and efficient detection method, realizing rapid dynamic response by providing sufficient energy for the load when the load current is suddenly increased.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: January 10, 2023
    Assignee: SHANGHAI BRIGHT POWER SEMICONDUCTOR CO., LTD.
    Inventor: Shun-Gen Sun
  • Patent number: 11509297
    Abstract: A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 22, 2022
    Assignees: SK hynix Inc., Korea University Research and Business Foundation
    Inventors: Minseop Lee, Hyunsu Park, Jincheol Sim, Chulwoo Kim
  • Patent number: 11487311
    Abstract: A method for providing a jitter signal for modulating a switching frequency of a power switch for a power converter. The method comprising receiving a drive signal representative of the switching frequency of the power switch, detecting the switching frequency from the drive signal, determining if the switching frequency is less than a first threshold frequency, and modulating a frequency of the jitter signal in response to determining if the switching frequency is less than the first threshold frequency.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: November 1, 2022
    Assignee: Power Integrations, Inc.
    Inventors: Giao Minh Pham, Lance M. Wong
  • Patent number: 11423971
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Patent number: 11411555
    Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Ee Wah Lim, Lay Leng Lim
  • Patent number: 11387813
    Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Hsiu-Hsien Ting, Po-Chun Huang, Yu-Li Hsueh
  • Patent number: 11381225
    Abstract: A single ended receiver includes a current mode logic circuit, a differential to single amplifier, and a voltage detector. The current mode logic circuit is configured to receive an input signal and a reference voltage value and is configured to output a first output signal. The differential to single amplifier is coupled to the current mode logic circuit and is configured to receive the first output signal and to output a second output signal. The voltage detector is coupled to the differential to single amplifier and is configured to output a control signal to the differential to single amplifier according to the reference voltage value. The differential to single amplifier is further configured to adjust a voltage value of the differential to single amplifier internal signal according to the control signal, so that a duty cycle of the second output signal is adjusted.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: July 5, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cong-An Lu, Shih-Cheng Hung
  • Patent number: 11356085
    Abstract: The PWM waveform generation device comprises a time-division multiplexing module, wherein the time-division multiplexing module is configured for receiving a first preprocessing signal and a second preprocessing signal output by two system clock sources, performing a first time-division processing on the first preprocessing signal to obtain a first time-division signal, and performing a second time-division processing on the second preprocessing signal to obtain a second time-division signal according to a preset strategy, performing multiplexing processing on the first time-division signal and the second time-division signal to obtain a PWM output signal, wherein an output frequency of the PWM output signal is a default standard clock frequency. The present invention has the advantages that the cycle length of one cycle of a PWM waveform depends on cycles of two preprocessing waveforms and the number of the cycles, such that the output waveform frequency may be calibrated to a desired frequency.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 7, 2022
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventors: Jian Hu, Bo Yang, Xuhua Zhang, Chaoyang Luo, Xingyu Chen
  • Patent number: 11356238
    Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 7, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Manish Bhardwaj, Venkataratna Subrahmanya Bharathi Akondy, Shamim Choudhury
  • Patent number: 11336267
    Abstract: Duty signal ratio and signal generation circuits with clock signal duty ratio stabilization under decreased power supply conditions are disclosed. In one example, a duty ratio correction circuit includes an inverting buffer, a capacitor, a low pass filter, an error amplifier, and an adjusting unit. The capacitor adjusts the rising and falling times of an inverted signal output from the inverting buffer. The low pass filter extracts a low frequency component of the inverted signal. The error amplifier adjusts a duty ratio of the inverted signal by controlling at least one of an output source current and an output sink current of the inverting buffer on the basis of a difference between the extracted low frequency component and a reference signal. The adjusting unit adjusts the control of the inverting buffer by the error amplifier.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 17, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazutoshi Ono, Nobuhiko Shigyo, Hideo Maeda, Toshio Suzuki, Yoshikatsu Jingu
  • Patent number: 11336265
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam
  • Patent number: 11329641
    Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Tai Sik Shin, Dong Shin Jo
  • Patent number: 11294419
    Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 11290096
    Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Tsung-Hsien Tsai
  • Patent number: 11276280
    Abstract: An in-vehicle apparatus includes a first pulse generator configured to generate a first pulse in accordance with predetermined equipment before a data stream transmitted from the equipment is received; a second pulse generator configured to generate a second pulse based on the received data stream; an output device configured to output a warning sound based on the first pulse or the second pulse; and a switching device configured to output the first pulse to the output device before the data stream is received, and output the second pulse to the output device as of when the first pulse and the second pulse coincide.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 15, 2022
    Assignee: ALPINE ELECTRONICS, INC.
    Inventor: Osamu Shinohara
  • Patent number: 11276444
    Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Tai Sik Shin, Dong Shin Jo
  • Patent number: 11264979
    Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Mao-Ruei Li, Ming Hsien Tsai, Ruey-Bin Sheen
  • Patent number: 11257531
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 11218141
    Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 4, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi
  • Patent number: 11159152
    Abstract: Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: October 26, 2021
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Chandrashekhar Reddy Ayya, Srishti Garg
  • Patent number: 11100967
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 11088681
    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11062781
    Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Zhen-Hong Hung, Shih-Yang Sun, Sheng-Wen Chen
  • Patent number: 11012061
    Abstract: A circuit includes a core circuit configured to receive an input clock and output and output clock in accordance with a control signal, the core circuit having an encoder configured to encode the control signal into a plurality of control words and a plurality of duty cycle correction buffers configured in a cascade topology and controlled by said plurality of control words, respectively; a duty cycle detection circuit configured to output a logical signal in accordance with a comparison of a duty cycle of the output clock with a target value; and a controller configured to output the control signal in accordance with the logical signal.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11005468
    Abstract: A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 11, 2021
    Assignee: Faraday Technology Corp.
    Inventors: Sivaramakrishnan Subramanian, Sridhar Cheruku, Sandeep Kumar Mohanta, Hussainvali Shaik
  • Patent number: 10998888
    Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongho Shin, Kyungtae Kang, Junha Lee, Tongsung Kim, Jangwoo Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 10983443
    Abstract: A control device actuates actuator unit to set a position of an optical element of a lithography system. The control device includes an amplifier unit for providing a control signal for the actuator unit via a voltage signal and a PWM signal. The PWM signal has a duty factor and a clock frequency. The control device also includes a modulator unit designed to provide the PWM signal having the duty factor and a defined clock frequency from a plurality of defined clock frequencies. A defined clock frequency of the plurality of defined clock frequencies is an integer multiple of a basic clock frequency. The basic clock frequency is in the range of 10 kHz to 1 MHz.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Stefan Krone, Lars Berger, Ralf Kiesel, Paul Wijlaars
  • Patent number: 10972078
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam