Abstract: A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).

Abstract: A phase detector includes a first selection circuit configured to select a first clock from a first group of clocks supplied to the first selection circuit and to transmit the first clock, and at least one phase comparator configured to detect a difference in phases between the first clock and a second clock supplied to the phase comparator and to transmit the difference as a scan signal.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: Provided is a pass gate circuit capable of operating stably in a transition phase of an input signal, a self-refresh circuit including the pass gate circuit, and a method of controlling the pass gate circuit. The pass gate circuit according to the present invention includes a pass gate unit and a pass gate control unit. The pass gate unit delays an input signal for a fixed duration and outputs the delayed input signal as an output signal in response to a switching control signal. The pass gate control unit outputs the switching control signal, and in response to an internal control signal, determines the existence of a transition in the input signal, and enables or disables the switching control signal according to the determination. The pass gate circuit, the self-refresh circuit including the same, and the control method of the pass gate circuit are capable of operating stably in the transition phase of the input signal.

Abstract: Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.

Abstract: The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (?Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectr

Abstract: A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

Abstract: A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop circuits to avoid the fight between a first node, or OUTBAR node, and the prior art back-to-back inverter keeper circuit. The result is a faster semi-dynamic flip-flop circuit that is also immune to noise.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.

Abstract: A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.

Abstract: An exemplary skew-tolerant true-single-phase-clocking (TSPC) flip-flop is disclosed that reduces current spikes by allowing willful introduction of skew in the clock tree of a single-phase circuit design. More precisely, a split-clock TSPC flip-flop, which allows the flip-flop hold times to be met in the face of skewed clocks, which, in turn, reduces the maximum value of current spikes, can be substituted for a traditional TSPC flip-flop in a sequential logic circuit. The input of the split-clock TSPC flip-flop is latched according to a first clock signal, which was used in a preceding stage, while the output of the split-clock TSPC flip-flop is driven according to a second clock signal. The first and second clock signals can be skewed in time, but have the same frequency and substantially the same phase. Metal Oxide Semiconductor (MOS) device can also be included within the split-clock TSPC flip-flop to reduce power dissipation in cases of large clock skew.

Abstract: A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle latches in conjunction with alternate power-gated circuitry, even when many stages are cascaded in a pipeline structure. The data state on a single forcing node can be passed through one or more cascaded latch stages as well as through additional circuitry. By forcing latch transmission gates to be conductive during standby mode, multiple stages can be set to a specific state, as determined by an earlier stage being set by a forcing transistor. A clock generation. circuit and method is also provided for controlling transmission gates within the latches.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

Abstract: A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.

Abstract: An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Abstract: A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A signal transfer clocking circuit is disclosed which features a first stage including a first latch and a first, non-clocking circuit in series therewith and a second stage including a second, dynamic latch and at least a second circuit in series therewith. The first latch has a data input side and is opened in response to a first level of a pulse clock signal applied thereto to effect transfer of incoming data through the first stage in a first phase of operation of the signal transfer clocking circuit.

Abstract: A temperature-sensing circuit includes a first circuit block outputting an output voltage having negative or positive temperature coefficients and a second circuit block amplifying the output voltage of the first circuit block to a predetermined amplitude and outputting the amplified output voltage. It further includes a third circuit block producing a voltage having temperature coefficients of a polarity opposite to that of the first circuit block and adding the produced voltage to the output voltage of the second circuit block to cancel out components of second order temperature coefficients contained in the output voltages of the first and second circuit blocks.

Abstract: A method and apparatus for testing pipelined dynamic logic makes it possible to set and retrieve values from dynamic logic pipelines that have no internal latches. A modification to the pipeline circuits and clocking circuitry enable scanning logic to set and retrieve values from the pipelined circuits.

Abstract: An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100 MHz to several GHz. The analog latch is used as a latching comparator for comparing a time-varying analog signal with an analog reference voltage. The latch uses CMOS manufacturing technology and a minimal amount of space for a two-stage amplifying and signal-generating device. The latch is useful in analog to digital converters (ADCs) in which high speed and high reliability are required, but only a small amount of space is available. The device is so small and economical that several may be used in series to avoid any meta-stability problems in high-speed read/write operations.

Abstract: A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: A semiconductor integrated circuit device includes connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state, and a second power supply circuit. The second power supply circuit generates a second power supply potential supplied to the source or drain of the cell transistor and starts operating following the start-up of the first power supply circuit after a power-on.

Abstract: A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.

Abstract: A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

Abstract: A semiconductor memory device, such as a virtual SRAM, includes a temperature detection module and a temperature characteristic regulation module. The temperature detection module has a temperature sensing element, which includes a specific pn junction area set in a cutoff state out of pn junction areas formed on an identical semiconductor substrate with a memory cell array and outputs a leak current running through the specific pn junction area. The temperature detection module detects a temperature change of the semiconductor memory device in response to the leak current output from the temperature sensing element. The temperature characteristic regulation module regulates a generation period of a refresh timing signal, which is used to determine an execution timing of a refreshing operation in the memory cell array, based on a result of the detection by the temperature detection module.

Abstract: A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic node keeper device through the strobe component output, the keeper device is active or conductive only when necessary to protect against noises in the pull down network for the strobe circuit. At all other times in the course of operation of the dynamic strobe circuit, the dynamic node keeper device according to the invention is nonconductive or inactive. Thus, the dynamic strobe circuit according to the invention reduces power consumption.

Abstract: An interface circuit, according to the present invention includes a frequency divider which divides a frequency of a base clock to provide frequency-divided clock signals; a first address register which stores an address signal at a timing in which the frequency-divided clock signal is turned to high; a second address register which stores the address signal at a timing in which the clock signal is turned to low; a first data register which stores a data signal at a timing in which the clock signal is turned to high; and a second data register which stores the data signal at a timing in which the clock signal is turned to low. The data signals stored in the first and second data registers are selectively outputted.

Abstract: An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

Abstract: A method for initializing or configuring an electrical circuit, is described. The method includes reading data units stored in a memory device, using data contained in a first data unit part of the data units as a specification for use of data contained in a second data unit part of the data units, and carrying out the initialization or the configuration of the electrical circuit in a manner dependent on a content of an initialization control register contained in the electrical circuit. And in that during the initialization of the electrical circuit, the data read from the memory device can be written once or more often to the initialization control register.

Abstract: In a flip-flop including a control element and a holding element, in which a first current causes the control element to set a logic state and a second current causes the holding element to maintain the logic state, the cut-off frequency is increased by dimensioning the transistors of the holding element to be smaller than the transistors of the control element. In other words the transistors of the holding element have a smaller current-carrying capacity than the transistors of the control element.

Abstract: A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.

Abstract: Undersired glitches in output signals from TSPC-1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.

Abstract: A memory control circuit includes a watching circuit for observing a first request signal from an external device for accessing to a RAM and a second request signal, which has a priority higher than the first request signal, from a CPU for accessing to the RAM. The memory control circuit further includes a control circuit having an OR gate, an AND gate and a NOR gate. When the first and second request signals are inputted, it is scheduled that an operation based on the second access request signal is performed by the control circuit prior to that based on the first access request signal.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: A single event upset (SEU) hardened latch circuit utilizing two cross-coupled inverters in which the voter output circuitry is fed back to the output node of the latch circuit.

Abstract: A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of the inverse of the evaluate clock is generated by a delay element. The delayed inverse of the evaluate clock is fed to the enable input of the latch. The input to the latch comes from static logic and the output of the latch is fed to the dynamic logic. The net result is a latch that is open until the evaluate clock is instructing the dynamic logic to evaluate, and remains closed until a delay element delay time after the evaluate clock instructs the dynamic logic to reset.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.