Abstract: A flip-flop circuit has a master circuit including a static flip-flop with a feedback loop, and a slave circuit including a dynamic flip-flop. In the flip-flop circuit, a clock signal is applied to the master circuit and the slave circuit. A clock width of the clock signal is determined by a time period from a clock edge for taking data into the master circuit to another clock edge for closing the master circuit, and is set to less than a given time period.

Abstract: A scan cell is described which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of circuitry to be scan tested. It functions only as a positive edge triggered latch when scan testing of a logic structure is to be performed.

Abstract: A scan flip-flop includes a data input, a scan input, a mode selection input, a mode control input and a clock input. When the mode selection input is set to a first selection value, and the mode control input is set to a first control value, the scan flip-flop operates as a D flip-flop. When the mode selection input is set to a second selection value, the scan flip-flop shifts in a scan input value on the scan input when one of the mode control input and the clock input is toggled. Also, as long as the mode selection input is set to the first selection value, and the mode control input is set to a second control value, the scan flip-flop holds a current value within the scan flip-flop.

Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.

Abstract: A bistable logic network of the sequential type, responsive to the edges of input signals, comprising first and second input SR flip-flops which are connected to an output SR flip-flop through two transfer and block logic gates.Each of said logic gates has two input terminals connected to the output terminal and to one input terminal of an input flip-flop.The output terminals of the output flip-flop are feedback connected to the other input terminals of the two input flip-flops.

Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.

Abstract: A cell for a shift register comprises an input and an output connected to the line with which it is associated, the cell being parallel-connected on this line, and the output of the cell being separated from the rest of this cell by a tristate buffer circuit. This cell is made in such a way that the state of the inputs of the flip-flop circuits of the cell is never floating when these cells are insulated from the inputs of the cell.

Abstract: A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively.

Abstract: A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Abstract: Digital circuitry in a data processing system includes parallel signature analysis circuitry having a sampling feature which permits sampling any given signal on all clock phases of the digital circuitry. The parallel signature analysis circuitry provides for selective coupling of a target node to each of the respective inputs of a pair of serially-coupled latches.

Abstract: A device which includes a plurality of master/slave stages, each master/slave stage includes a master segment and at least one slave segment. Each master segment (excluding the one including a first master/slave stage) may be actuated by either external logic during normal operation, or by the output of a preceding slave segment during a scan operation. A continuous single phase clock provides clocked signals to a scan port, as well as the master segment and the slave segment in each of said master/slave stages. A control portion deactivates logic applied to the master segments, and actuates logic applied from the scan port to said master segments during all scan enable periods. The control portion also deactivates the scan port from the master segment, and activates the logic output to the master segments during all normal operation periods.

Abstract: A high speed bi-polar D latch circuit uses cross-coupled current-biased buffering transistors to block control current from output resistors so that the clock and data controls are not connected directly to the outputs of the latch. The memory cell portion of the latch which controls the latch output is constantly biased. Latch output swing is minimally affected by clock/data switching due to the buffering action of the emitter followers on the latch outputs. Changing the latch state is accomplished by changing the base-emitter voltage of the buffering transistors through the emitter followers. The circuit provides greater noise immunity at latch outputs during clock transitions and faster rise/fall times of output waveforms.

Abstract: A synchronizing means is provided for synchronizing an asynchronous interrupt signal to a synchronous clock signal for a computer system or the like. The synchronizing means includes a plurality of latch subsystems, where each of the latch subsystems has a sample input terminal for receiving a synchronous clock signal and a hold terminal for receiving a complementary synchronous clock signal. Set logic means are provided for generating a set output signal in response to certain predetermined output signals of the synchronizing means having a predetermined relationship therebetween, which occurs when an input interrupt signal has a duration greater than 1.5 periods of the synchronous clock signal. The set logic means includes AND gates and OR gates. Reset logic means are provided for generating a reset output signal. The reset logic means includes AND gates and OR gates.

Abstract: A flip-flop circuit includes a first switch for controlling passing of input data in response to a single clock signal, a first inverter for inverting the data passed through the first switch, a second inverter for inverting the data output from the first inverter into inverted data and for inputting the inverted data to the first inverter, a second switch for controlling passing of the data output from the first inverter in response to the single clock signal, a third inverter for inverting the data passed through the second switch, and a fourth inverter for inverting the data output from the third inverter into inverted data and for inputting the inverted data to the third inverter, where the first inverter has a driving capability larger than that of the second inverter, and the third inverter has a driving capability larger than that of the fourth inverter.

Abstract: A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Abstract: A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.

Abstract: A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/compliment generator circuit (TCG) for generating a data and its compliment from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.

Abstract: A flip-flop circuit which has a low power requirement and is capable of high-speed operation has first and second latch circuits having respective clock input terminals connected respectively to inverted- and normal-phase clock input terminals, a pair of differential data input terminals connected respectively to the differential signal input terminals of the first latch circuit, a pair of differential output terminals connected respectively to the differential signal output terminals of the second latch circuit, and a power supply and a current source, each connected to the first and second latch circuits. Each of the first and second latch circuits has first and second current mirror circuits energizable by the power supply, and first through fifth MOS transistors, each of the first and second latch circuits being of a dynamic type.

Abstract: Adverse visual effects on a video display caused by switching operations in a digital-to-analog converter of the video subsystem and by parasitic impedance loading the DAC are minimized. Current cells associated with the DAC generate discrete currents for the video display. Each current cell has a current source for providing a current continuously and first and second switching mechanisms. The first switching mechanism is actuated by a select signal for switching the current to a current sink having a dummy resistance R.sub.d, and the second switching mechanism is actuated by an nselect signal for switching the current to the video display. The select and nselect signals, are generated from input data. A first feedback loop combines the select signal with the data to derive the nselect signal so that the nselect signal is generated after the select signal decreases to a predefined threshold, preferably zero.

Abstract: A master-slave differential comparator having a threshold value. The master section controls the threshold value of the slave section. The slave section is controlled by bias currents therein to matching same in the master section. The bias currents are substantially determined by fixed biases applied to the master section, the difference in biases being substantially equal to the threshold value of the comparator.

Abstract: A flip-flop has both a system output and a scan output. A system output signal for the flip-flop is placed on the system output. When the flip-flop is in a normal operating mode, a scan output signal on the scan output is held at a static logic level. When the flip-flop is in a scan mode, the scan output signal on the scan output transitions between logic 1 and logic 0 synchronous with transitions of the system output signal on the system output.

Abstract: A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).

Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.

Abstract: A novel RS latch for use in asynchronous designs has been provided. The RS latch is made scannable by the use of additional circuitry which provides a basis for a scan chain signal to propagate in and out the scannable RS latch. Such a scannable RS latch greatly facilitates the testing of the asynchronous design.

Abstract: A bistable flip-flop with reset control is provided. The flip-flop includes a storage cell having a first inverter whose input can receive a write signal from an input signal delivered to the input terminal of the first inverter, and a second inverter which is feedback-mounted with respect to the first inverter. The flip-flop also includes a first switch controlled by a reset signal for enforcing a specified logic state at the input of the first inverter when the reset signal is active, and a second switch controlled by the reset signal so as to prevent the first inverter from receiving a write signal in a logic state opposite to the specified state when the reset signal is active.

Abstract: A 2-level logic `current injection` circuit topology suitable for heterojunction bipolar transistor (HBT) technology. The circuit requires lower supply voltage headroom and demonstrates smaller propagation delay than conventional 2-level emitter coupled logic/current mode logic (ECL/CML). Master-slave flip-flop circuits have been fabricated in AlGaAs/GaAs, HBT. Test results indicate that the circuits are fully functional at 10 Gbit/s and an operating clock frequency as high as 20 GHz is recorded.

Abstract: A programmable hold-off circuit for an integrated circuit for selectively providing hold-off for outputs of the integrated circuit. The programmable hold-off circuit includes a hold-off latch for receiving an output signal from the interior logic of the integrated circuit, and for providing a hold-off latch output, an output buffer responsive to hold-off latch output for providing a buffered output, a hold-off control circuit responsive to a hold clock for controlling the hold-off latch to be continuously transparent when the hold-off control circuit is programmed for no hold-off, and for controlling the hold-off latch pursuant to the hold clock when the hold-off control circuit is programmed for hold-off. The hold-off control circuit is programmed, for example, pursuant to a boundary scan flip-flop.