Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.

Abstract: A vehicle communication system for communicating with a person who is within a vehicle includes a device for hearing audible noises that emanate within the vehicle at locations external to the vehicle without making physical contact with the vehicle. Communication from the person in the vehicle to a person external to the vehicle is performed by aiming a light beam from the vehicle and receiving reflections of the light beam. The light beam is modulated by vibration of the vehicle caused the audible noises from within the vehicle. The received light beam is then processed to reproduce the audible noises so that the audible noises can be heard from a location outside of the vehicle, even when the vehicle is sealed (windows closed, etc.).

Abstract: A power distribution system includes the use of a master digital signal processor (DSP) and two slave DSPs connected to the master DSP. The slaves DSPs may be connected to each of a plurality of solid state power channels (SSPC) controlling power distribution functions to each of the channels. A power control strategy may use one power supply for the master DSP, a second power supply shared between the slave DSPs, and a third power supply shared between each of the SSPC channels.

Abstract: A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair.

Abstract: A master stage 101 comprises a differential circuit composed of transistors 1 and 2, a differential circuit composed of transistors 3 and 4, a differential circuit composed of transistors 5 and 6, a load circuit 7 (a first load circuit), a load circuit 8 (a second load circuit), and a current source transistor 9. The load circuit 7 (the first load circuit) is composed of an inductor 7A (a first inductor), an inductor 7B (a fifth inductor), and a capacity 7C (a first capacity). The inductor 7B and capacity 7C cooperates together in forming a parallel resonance circuit (a first LC parallel resonance circuit), while the parallel resonance circuit is connected in series to the inductor 7A.

Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: An dielectric laminated filter improves a skirt characteristic to shift am attenuation pole to a transmitting frequency band while maintaining the same band width of the transmitting frequency band and includes a dielectric block laminated with a plurality of dielectric sheets, ground electrodes formed on front and rear sides of the dielectric block, input and output electrodes formed on both sides of the dielectric body to be separated from the ground electrodes, an inductor pattern having two portions disposed parallel to the resonator patterns coupled to the input and output electrodes and a connecting portion coupling the two portions to induce an inductance coupling with the resonator patterns coupled to the input and output electrodes to improve a filter response characteristic by adjusting the inductance coupling.

Abstract: A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

Abstract: A master-slave flip-flop circuiting having transistors connected in cascade in two stages between a power supply and ground. A clock differential amplifier, a master flip-flop, a slave flip-flop, and a waveform-shaping amplifier are all connected mutually in parallel to a power supply. High-speed operation at a minimum operation power supply voltage is achieved.

Abstract: A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.