Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Abstract: A semiconductor device has stored therein a plurality of bits of fixed data. The semiconductor device includes a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output the value of each bit received at an input terminal of each of the memory elements according to a timing signal. An initialization control unit feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal, each of the plurality of memory elements being initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.

Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.

Abstract: Instructions indicative of changing a view of a virtual object may be received by a device. At least a portion of the virtual object may be viewable from a viewpoint that is at a given distance from a surface of the virtual object. The device may cause a change of the view along a rotational path around the virtual object in response to the receipt of the instructions based on the given distance being greater than a threshold distance. The device may cause a change of the view along a translational path indicative of a shape of the surface of the virtual object in response to the receipt of the instructions based on the given distance being less than the threshold distance.

Abstract: A semiconductor circuit and a semiconductor circuit layout system are provided. The semiconductor circuit includes a clock inverter which inverts a clock signal and outputs an inverted clock signal where the clock inverter is laid out between a second master latch main circuit configured to latch signals of a first node and a fourth node based on the clock signal and the inverted clock signal, respectively, and a second slave latch main circuit configured to latch signals of a second node and a fifth node based on the clock signal and the inverted clock signal, respectively.

Abstract: An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.

Abstract: Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.

Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

Abstract: Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a passgate, a passgate inverter, a leakage compensation unit, and an inverter. The passgate may be coupled between a flip-flop data input terminal and a first node. The passgate inverter and the inverter may be sequentially connected between the first node and a flip-flop data output terminal. The leakage compensation unit may be connected between the first node and the flip-flop data output terminal parallel to the passgate inverter and the inverter.

Abstract: A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for arranging configurable logic circuits such that the configurable logic circuit may be configured to form one or more of several logic circuits by coupling a combination of nodes included in the logic circuit. Configuring the configurable logic circuit may include modification of a single wiring layer.

Abstract: An aspect of the disclosure includes a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of an output signal of the first amplifier circuit in response to a high signal level at the output of the second amplifier circuit, and configured to cause a second predetermined signal level shift of an output signal of the first amplifier circuit in response to a low signal level at the output of the second amplifier circuit.

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

Abstract: During a period in which a first signal S1 and second signal S2 are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal SOUT that changes level when the capacitor voltage crosses a predetermined threshold value VTH. Each circuit unit includes a resistor Rg and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S1 is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S2 is the second level and the corresponding bit of the input code is a second value.

Abstract: Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages.

Abstract: Provided are a display device, a scan driver, and a method of manufacturing the same. A scan driver includes: a level shifter configured to output a power and a signal, and a scan signal generating circuit configured to generate a scan signal based on the power and the signal supplied from the level shifter, the scan signal generating circuit including a buffer configured to transmit a clock signal to a stage of a shift register, the buffer including two inverters, one of the two inverters being included in a multi-buffer.

Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

Abstract: A readout circuit for use with an image sensor includes a comparator coupled to compare a ramp signal from a ramp generator with an output signal from a pixel of a pixel array. A counter is coupled to the comparator to count until the comparator detects that a ramp signal value has reached an output signal value. The counter includes K cascade-coupled dynamic flip-flop circuits to generate the K least significant bits (LSBs) of the N-bit output of the counter. The counter also includes N-K cascade-coupled static flip-flop circuits to generate the N-K most significant bits (MSBs) of the N-bit output of the counter. A latch is coupled to the counter to store a count value generated by the counter after the ramp signal value has reached the output signal value.

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a logic circuit and a memory macro. The memory macro includes: a memory cell array including a memory bit cell; an output buffer; a sense amplifier configured to output data read from the memory cell array based on a first clock signal; a write driver configured to apply a write voltage; and a first register circuit that configured to fetch first input data based on a second clock signal, output the first input data to the write driver based on the second clock signal in a write operation, and outputs the first input data to the output buffer based on the first clock signal in a scan test of the logic circuit.

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

Abstract: Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.

Abstract: A shift register comprises an input unit, an output unit, a scan direction selecting unit and a data latching unit. The scan direction selecting unit is connected to a forward-scan signal input terminal, a backward-scan signal input terminal, a positive input terminal, an inverse input terminal and the data latching unit. The input unit is connected to a first clock signal input terminal, the forward-scan signal input terminal, the backward-scan signal input terminal, a low-level signal input terminal and the data latching unit. The data latching unit is connected to a reset signal input terminal, the input unit, the output unit, the scan direction selecting unit, and a high-level signal input terminal. The output unit is connected to a second clock signal input terminal, the data latching unit, the low-level signal input terminal, the high-level signal input terminal, the reset signal input terminal, and a signal output terminal.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract: A flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.

Abstract: An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.

Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

Abstract: A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

Abstract: A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Abstract: A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.

Abstract: A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.

Abstract: A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

Abstract: Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset signal. The multiplexer may also receive a normal clock signal and a delayed clock pulse signal that is triggered in response to detecting assertion of the reset signal.

Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.