Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

Abstract: When a bias voltage of a substrate is generated, an output voltage of a charge pump is controlled at an appropriate level, resultingly reducing a consumption current. The charge pump generates a predetermined output voltage from a predetermined DC power supply. A clock generator outputs a clock for operating the charge pump. A voltage monitoring unit monitors the output voltage of the charge pump and controls the clock output from the clock generator such that the output voltage is maintained within a predetermined range. A voltage regulator generates the bias voltage from the output voltage of the charge pump.

Abstract: A comparator circuit configured to output an output voltage at a first logic level, upon an input voltage exceeding a first threshold voltage, and output the output voltage at a second logic level, upon the input voltage dropping below a second threshold voltage lower than the first threshold voltage. The comparator circuit includes a converter circuit configured to convert the input voltage of the comparator circuit into a first voltage and a second voltage lower than the first voltage, and a logic circuit configured to output a voltage, as the output voltage of the comparator circuit, that is at the first logic level, upon the first voltage exceeding a third threshold voltage, and at the second logic level, upon the second voltage dropping below a fourth threshold voltage lower than the third threshold voltage.

Abstract: A photodetector array (1) is provided comprising a plurality of pixels (10ij) between a supply line (4j) and a common electrode (2). Respective pixels (10ij) comprise a photon radiation sensitive element (11ij) arranged in a series connection with a switching element (20ij) characterized in that the series connection further includes a resistive element (30ij).

Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

Abstract: An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.

Abstract: Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.

Abstract: Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.

Abstract: An input circuit includes a first input transistor and a second input transistor connected to an input terminal; a current source which makes a current flow in the second input transistor through a current mirror; a switch provided between the current mirror and the current source, and having a switch control terminal connected to the drain of the first input transistor; and a transistor connected to the first input transistor, on/off of the transistor being controlled by an output signal, wherein a current drivability of the second input transistor is switched by an output signal, and a threshold voltage to the input signal is determined based on the current drivability of the second input transistor and the current source.

Abstract: Circuits and methods for balancing Bias Temperature Instability (BTI) are disclosed. An inverter circuit comprises an inverter input node configured to receive an inverter input signal, wherein the inverter input node is coupled to gates of an inverter pair, wherein the inverter pair includes an inverter pair n-type metal-oxide-semiconductor (NMOS) transistor and an inverter pair p-type metal-oxide-semiconductor (PMOS) transistor, an inverter output node configured to provide an inverter output signal, wherein the inverter output signal is an inversion of the inverter input signal, and at least one balancing transistor configured to balance a voltage at a source of the inverter pair PMOS, a source of the inverter pair NMOS, or any combination thereof.

Abstract: The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.

Abstract: A circuit includes a first resistor coupled to a supply voltage node. The circuit further includes a first pair of transistors and a second pair of transistors. The first pair of transistors is coupled in series between the first resistor and an output node. The second pair of transistors is coupled in series between the output voltage node and a ground nod. A first capacitor is coupled in parallel across the first resistor.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.

Abstract: To provide an input circuit which avoids power supply voltage dependency of a threshold of the input circuit when an output signal is transited. There is provided an input circuit equipped with an input transistor and a current source connected in series between a first power supply and a second power supply. The input circuit is configured in such a manner that an input signal is inputted to a gate of the input transistor and a signal of a connection point between the input transistor and the current source is outputted as an output signal, and a current value of the current source is changed based on the output signal.

Abstract: An inverter circuit includes: a first P-channel MISFET having a source connected to a positive-side terminal and a drain connected to an output terminal; a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal; a first delay element connected between a gate of the first P-channel MISFET and an input terminal to which an input signal is supplied; first switch element connected in parallel with the first delay element between the input terminal and the gate of the first P-channel MISFET; a second delay element connected between the input terminal and a gate of the first N-channel MISFET; and a second switch element connected in parallel with the second delay circuit between the input terminal and the gate of the first N-channel MISFET. The first and second switch elements operate in response to a potential on the output terminal.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Abstract: A Schmitt trigger circuit includes a first inverter, second inverter, first feedback unit, and second feedback unit. The first inverter includes a PMOS transistor unit and an NMOS transistor unit which generate an internal signal by inverting an input signal based on a first feedback signal and provide the internal signal to a first node. A second inverter generates an output signal by inverting the first signal. A first feedback unit generates a first feedback signal providing a first hysteresis character to a first unit among the PMOS transistor unit and NMOS transistor unit based on a first signal of the first node. A second feedback unit generates a second feedback signal providing a second hysteresis character to a second unit among the PMOS transistor unit and NMOS transistor unit based on the output signal. The second feedback unit provides the second feedback signal to the first node.

Abstract: In a DC/DC converter, a driving method thereof, and a power supply using the same, the DC/DC converter includes a plurality of power switches connected as a serial string between an input terminal and a ground terminal, a first capacitor connected to at least two power switches of the serial string in parallel, an inductor connected between an intermediate node of the serial string and an output terminal, a second capacitor connected between the output terminal and the ground terminal, and a plurality of drivers configured to generate a switching control signal for each of the plurality of power switches. A voltage having no correlation with a voltage of the input terminal is supplied to a power terminal of each of the plurality of drivers.

Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Abstract: A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.

Abstract: A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit; wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

Abstract: A latch-based level-shifter is provided that includes an edge-triggered pulse generator that drives a switch to switch off and isolate a pair of cross-coupled inverters in the level-shifter from ground for a transition period responsive to rising and falling edges in an input signal.

Abstract: Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

Abstract: A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.

Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

Abstract: A triple-balanced mixer is disclosed. The mixer features a complementary metal oxide semiconductor (CMOS) mmW (millimeter wave) integrated circuit and adds an inverted double balanced mixer to a double-balanced Gilbert cell mixer to provide a triple-balanced mixer. Another term for this type of mixer is doubly double balanced. Pairs of field effect transistor (FET) devices are interleaved into a single device. The inverted mixer provides an inverted LO feedthrough signal equal in amplitude to the LO feedthrough from the first mixer. The inverted LO feedthrough is used to cancel the LO feedthrough, or leakage, of the first mixer at the RF port.

Abstract: A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.

Abstract: An apparatus comprises at least one transistor configured as analog switch, a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor, and a comparator circuit in electrical communication with the well biasing circuit and the transistor. The comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor. The well biasing circuit is configured to apply a first electrical bias to the bulk region of a transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions.

Abstract: A wheel hub drive system with an electric motor that can be arranged inside a wheel rim, whereby the electric motor is formed by rotor that is at least indirectly joined to a wheel hub and by means of a stationary stator that can be supplied with alternating current. With an eye towards obtaining more space for the vehicle occupants, it is proposed to arrange the converter with its entire power electronics unit on the stator so that the wheel hub drive system can be operated with direct current from the battery of the vehicle, or else no alternating current lines have to be laid in the vehicle. Consequently, the alternating current is generated by the converter that is arranged in a converter housing attached axially next to the stator.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: A resistive switching element can be used in a nonvolatile digital Schmitt trigger circuit or a comparator circuit. The Schmitt trigger circuit can include a resistive switching circuit, and a reset circuit. The resistive switching circuit can provide a hysteresis behavior suitable for Schmitt trigger operation. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The comparator circuit can include a resistive switching circuit, a reset circuit, and a threshold setting circuit. The resistive switching circuit can include a resistive switching element, and can be operable to provide a signal comparing an input voltage with the set or reset threshold voltage of the resistive switching element. The threshold setting circuit can be operable to modify the set or reset threshold of the resistive switching element, effectively changing the reference voltage for the comparator circuit.

Abstract: An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an I/O cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode. The retention control cell circuit latches the retention enable signal and outputs a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for input/output (I/O). And, the I/O cell circuit latches data based on the retention control signal.

Abstract: An inverter is capable of improving the reliability of driving. The inverter includes a first transistor and a second transistor. The first transistor is coupled between a first power source and an output terminal of the inverter, and has a first gate electrode coupled to a first input terminal of the inverter and a second gate electrode coupled to a third power source. The second transistor is coupled between the output terminal and a second power source, and has a first gate electrode coupled to a second input terminal of the inverter and a second gate electrode coupled to the third power source.

Abstract: A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.

Abstract: A dynamic hysteresis comparator has a threshold voltage level with dynamic hysteresis for sensing small changes in differential input signals at the input, while controlling a duration that an output voltage state will remain fixed for preventing the output of the comparator from changing state in an unstable fashion or “chattering”. The comparator has a dynamic hysteresis circuit connected to an output of a trigger circuit of the comparator that detects when a decision is made that a first input of the comparator is greater than or lesser than a second input of the comparator causing an output of the comparator to change state. Once the decision causing the change of state of the output is detected, any decisions determining that second input is now lesser than or greater than the first input are prevented from causing the output of the comparator from changing state for a fixed time period.

Abstract: A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Abstract: A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Abstract: A buffer circuit includes a first inverter circuit that inverts an input signal, a second inverter circuit that inverts the output signal of the first inverter circuit, an impedance element connected between the first inverter circuit and the second inverter circuit, a first conductivity type switching element that increases a potential of the output node of the second inverter circuit when the input signal exceeds a first threshold voltage, and a second conductivity type switching element that decreases a potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.

Abstract: Schmitt trigger with rail-to-rail or near rail-to-rail hysteresis. In some embodiments, a method includes switching an output of a Schmitt trigger from a first logic state to a second state in response to an input meeting a threshold, where the threshold is applied to a first transistor of a first doping type and the input is applied to a second transistor of the first doping type, the first and second transistors operably coupled to each other through a current mirror of a second doping type. The first doping type may be an n-type, the second doping type may be a p-type, and the threshold may be a rising threshold having a value within 10% of a supply voltage. Alternatively, the first doping type may be a p-type, the second doping type may be an n-type, and the threshold may be a falling threshold having a value within 10% of ground.

Abstract: An input circuit includes a first P-channel MOS transistor including a first terminal supplied with a high-potential power supply voltage and a second terminal coupled to a first node, a second P-channel MOS transistor including a first terminal coupled to the first node and a second terminal coupled to a second node, a first N-channel MOS transistor including a first terminal coupled to the second node and a second terminal coupled to a third node, and a second N-channel MOS transistor including a first terminal coupled to the third node and a second terminal supplied with a low-potential power supply voltage. An input signal is supplied to gate terminals of the P-channel MOS transistors and the N-channel MOS transistors. A control circuit controls the potential at the first node and the potential at the third node based on the input signal and the potential at the second node.

Abstract: A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor.

Abstract: Presented systems and methods facilitate efficient switching operations for components operating at different voltage level than a received signal voltage level. In one embodiment, the components of a presented system are operable to perform switching operations for signals with a voltage level swing larger than the power rail of the circuit receiving the signals. In one embodiment a system includes an input component, a transition component, a transition point feedback component and an output component. The input component is operable to receive an input signal. The transition component is operable to transition the input signal. The transition point feedback component is operable to adjust a point at which a transition in the input signal occurs in the transition component. The output component is operable to forward an output signal from the transition point feedback component.

Abstract: A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.

Abstract: According to a novel aspect, operating an analog rail-to-rail comparator circuit with common mode detection of differential input signals includes generating a hysteresis current for the comparator circuit based on a common mode voltage used for the common mode detection. The hysteresis current is added to a differential output of a comparator in the comparator circuit, such that a hysteresis voltage at an output of the comparator circuit is substantially independent of the common mode voltage.

Abstract: One aspect of the present invention is directed to a circuit that includes an amplifier circuit disposed between an isolation link and a Schmitt trigger circuit to amplify a differential signal communicated over the isolation link and supply the amplified signal to the Schmitt trigger circuit. In turn, the Schmitt trigger circuit is coupled to the amplifier circuit to receive the differential signal and to supply a differential output signal corresponding to the differential signal communicated over the isolation link.

Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

Abstract: A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

Abstract: According to a novel aspect, operating an analog rail-to-rail comparator circuit with common mode detection of differential input signals includes generating a hysteresis current for the comparator circuit based on a common mode voltage used for the common mode detection. The hysteresis current is added to a differential output of a comparator in the comparator circuit, such that a hysteresis voltage at an output of the comparator circuit is substantially independent of the common mode voltage.