Abstract: According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Abstract: A comparator has a first input, a second input, an output, a control electrode of a first hysteresis transistor coupled to the output, and a control electrode of a second hysteresis transistor coupled to the output. A method for testing the comparator includes: reconfiguring the comparator to be an amplifier with unity gain feedback; providing an input voltage to the input; providing a first voltage to the first hysteresis transistor to provide a first offset voltage; measuring a first output voltage at the output; removing the first voltage from the first hysteresis transistor; providing the first voltage to the second hysteresis transistor; and measuring a second output voltage at the output.

Abstract: A dual data rate flip-flop circuit for reducing single event upset errors in the flip-flop circuit including two or more latch circuits connected in parallel. The latch circuits each have a clock input, data input, and latch circuit output. The dual data rate flip-flop circuit also includes a C-element, which has a plurality of inputs and a C-element output. The outputs of the latch circuits are provided to inputs of the C-element, and a keeper circuit is connected to the C-element output. An output buffer inverter connects to the C-element output and has an output corresponding to the dual data rate flip-flop circuit output.

Abstract: There are provided a Schmitt trigger circuit that has hysteresis characteristics in which a release point and an operating point are determined based on a width of an inputted pulse.

Abstract: High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

Abstract: A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

Abstract: There are provided a Schmitt trigger circuit that has hysteresis characteristics in which a release point and an operating point are determined based on a width of an inputted pulse.

Abstract: A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

Abstract: This application discloses a device that has a power-on reset generator. The power-on reset generator can include a power-on detector that receives an input electrical signal and outputs a digital signal that has predetermined value when the voltage of the input electrical signal exceeds a threshold voltage. The power-on detector can include multiple voltage-shaping elements arranged in series. Each voltage-shaping element can have a P-channel transistor and an N-channel transistor that differs in strength with respect to the P-channel transistor. The power-on detector can also include a switch that locks the digital signal at the predetermined value when the voltage of the input electrical signal exceeds the voltage threshold. In addition to the power-on detector, the power-on reset generator can include a digital delay that receives both the digital signal and a clock signal.

Abstract: Example embodiments are directed to a receiver for reducing ISI of at least one data transmission channel and compensating for signal gain loss, and method thereof. A receiver may include a high pass filter and a Schmitt trigger controlled by a plurality of first control signals and a plurality of second control signals. The plurality of first control signals and the plurality of second control signals may be used to shift a first trigger voltage and a second trigger voltage of the Schmitt trigger. A method of reducing intersymbol interference and compensating for signal gain loss of a receiver connected to at least one data transmission channel is also provided.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 to 103) and an inverter (501)); and a circuit for obtaining a large hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 and 104) and the inverter (501)).

Abstract: A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

Abstract: An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.

Abstract: A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract: A mechanism is provided for a one card to filter false signals due to a another card being hot-plugged. A discriminator circuit in the card receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal.

Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Abstract: A semiconductor integrated circuit comprises: a latch circuit constituted with a drive inverter and a feedback inverter so as to be connected in a cyclic form, wherein at least one of the drive inverter and the feedback inverter comprises a MOS transistor; and a current source connected to at least one of latch nodes of the latch unit. The magnitude relation of electric current flown in the MOS transistor and electric current flown in the current source is judged based on presence or absence of inversions in data values latched in the latch node.

Abstract: Techniques reduce the effects of power supply noise on a signal provided by a single-ended complementary metal-oxide semiconductor (i.e., CMOS) input buffer circuit capable of receiving an input signal having one of a variety of acceptable formats, while generating the signal to have substantially the same duty cycle as the input signal. The techniques include one or more of AC coupling, hysteresis, and voltage biasing applied to the input buffer circuit.

Abstract: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: A pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

Abstract: The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: Embodiments of the invention relate to a signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal. Advantageously, the signal receiver according to embodiments of the invention comprises a conversion stage inserted between the first and second voltage references and connected between the first and second input terminals of the signal receiver and an input terminal of an hysteresis comparator, connected in turn to the output terminal of the signal receiver. In particular, the conversion stage performs a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by the hysteresis comparator.

Abstract: A semiconductor integrated circuit includes a first external terminal for receiving a voltage converted by a resistance portion from a current varying in response to an extrinsic factor, a second external terminal for externally outputting the voltage received at the first external terminal as a detection signal, a control circuit outputting a control signal for changing a resistance value of the resistance portion based on the voltage received at the first external terminal, and a third external terminal for outputting the control signal to the resistance portion.

Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: A Schmitt trigger circuit having at least eight transistors is provided. The first transistor can have a source connected to a power terminal, and the second transistor can have a source connected to a drain of the first transistor. The third transistor can have a source connected to the drain of the first transistor, and the fourth transistor can have a source connected to a drain of the third transistor and a drain electrically connected to a ground terminal. The fifth transistor can have a drain connected to a drain of the second transistor, gates of the third and fourth transistors, and an output terminal. The sixth transistor can have a drain connected to a source of the fifth transistor and a source connected to the ground terminal. The seventh transistor can have a source connected to the source of the fifth transistor and a gate connected to the output terminal.

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.

Abstract: A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, and outputs both a first output data and a second output data based on both the first input data and the second input data, while the data holding unit holds both the first output data and the second output data. Both the first input data and the second input data are differential signals, and both the first output data and the second output data are differential signals that have phases that are inverted.

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract: Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting part 14 detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit 10 corresponding to potential VB of node NB, and it controls activation/deactivation of inverter 50 on the signal transmission path.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.

Abstract: A comparator includes a differential amplifier, and a hysteresis circuit. The differential amplifier amplifies a difference signal corresponding to a difference between input signals. The hysteresis circuit sets up a first transition threshold voltage and a second transition threshold voltage where the second transition threshold is different from the first transition threshold voltage. The hysteresis circuit generates a second signal that makes transition at the first transition threshold voltage when the difference signal changes in a first direction, and makes transition at the second transition threshold voltage when the difference signal changes in a second.

Abstract: A comparator includes a differential amplification circuit having differential input transistors and load transistors, an output transistor for outputting an output value of the comparator, a diode having a cathode connected to a ground, a current output circuit, a resistor connected between an anode of the diode and the bases of the load transistors. When the output transistor is in the OFF state, the diode clamps the voltage of the resistor to a forward voltage so that no current flows through the resistor. When the output transistor is in the ON state, the resistor has a slight voltage so that a slight current flows through the resistor. Thus, a threshold voltage of the comparator has a slight hysteresis without increase in resistance of the resistor.

Abstract: A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs (MN4, MN5) providing feedback from the circuit output to an input device (MN1) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.