Including Enhancement And Depletion Devices Patents (Class 327/209)
  • Patent number: 8742964
    Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 3, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan Adam Kleks, Ion Opris, Justin Seng
  • Patent number: 8233306
    Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Patent number: 8138775
    Abstract: A CMOS-controlled printhead sense circuit includes a CMOS control circuit module operable as a transmission gate switchable between first and second signal levels and a CMOS sense circuit module operable in a printhead sense mode in response to the CMOS control circuit module being switched to the first level and in a transparent mode in response to the control circuit module being switch to the second level. The CMOS control circuit module includes a combination of PMOS and NMOS FETs which define a CMOS switchable transmission gate. The CMOS sense circuit module includes a combination of PMOS and NMOS FETs which define respectively a switch device switchable between high and low states corresponding to the sense and transparent modes and a load enhancement device for the switch device.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: March 20, 2012
    Assignee: Lexmark International, Inc.
    Inventor: Ian David Tomblinson
  • Patent number: 7924056
    Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: April 12, 2011
    Assignee: ARM Limited
    Inventors: Nidhir Kumar, Sandeep Dwivedi, Tippana Hari Babu
  • Publication number: 20090195284
    Abstract: Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 6, 2009
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 7501871
    Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: March 10, 2009
    Assignee: NXP B.V.
    Inventors: Mihai Adrian Tiberiu Sanduleanu, Eduard Ferdinand Stikvoort, Idrissa Cissé
  • Patent number: 7489174
    Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 10, 2009
    Assignee: Sony Corporation
    Inventor: Atsushi Yoshizawa
  • Patent number: 7425855
    Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: September 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: David Jia Chen, Eugene James Nosowicz
  • Patent number: 7319353
    Abstract: An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal drives a first output high via a circuit. That first output going high, after a delay, drives a second output high. When the input goes low, a second steering FET controlled by the input signal drives the second output low. That second output going low, after a delay, drives the first output low. No latching is provided in the present invention.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: January 15, 2008
    Assignee: Fairchild Semiconductor Co.
    Inventor: Steven M. Macaluso
  • Patent number: 7265582
    Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: September 4, 2007
    Assignee: TPO Displays Corp.
    Inventors: Wei-Jen Hsu, Ming-Dou Ker, Ying-Hsin Li, An Shih
  • Patent number: 7002388
    Abstract: The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (?Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectr
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: February 21, 2006
    Assignee: Matsushita Electric Co., Ltd.
    Inventors: Takashi Nishikawa, Kenji Toyoda, Takashi Ohtsuka
  • Patent number: 6838920
    Abstract: An enveloping curve generator that guarantees one curve will overlap another when both are going high and the other overlaps the first when both are going low. When the input goes high, one steering FET is turned off and the other directs the input signal to drive an output high. That output going high after a delay drive the second output high. The second output being high latches the states of the two outputs high. When the input goes low, the off FET is turned on and the on FET is turned off. The input signal is directed to drive the second output low and after a delay the first output is driven low. The first output going low latches the states of the two outputs low.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: January 4, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Pravas Pradhan
  • Patent number: 6087872
    Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: July 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hamid Partovi, Robert C. Burd, Udin Salim, Frederick Weber, Luigi Di Gregorio, Donald A. Draper
  • Patent number: 6075748
    Abstract: An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: June 13, 2000
    Assignee: Mosaid Technologies Incorporated
    Inventor: Gurpreet Bhullar
  • Patent number: 5763960
    Abstract: A method and apparatus for sequencing the operation of electronic circuits based upon the level of the voltage provided by an external power supply. One or more power supply sequencer circuits may be interposed between an external power supply and one or more electronic circuits. The power supply sequencer circuits comprise a transistor having its high current node coupled to an external power supply, its controlling node coupled to a voltage sequencing means such as a diode and a resistor, wherein the resistor is in turn coupled to the external power supply and the diode is coupled to the ground potential. The transistor has its controlled high current node coupled through a power input node to the power input for the electronic circuit to condition the voltage received thereby. The power input node is in turn coupled through a second resistor to ground potential.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: June 9, 1998
    Assignee: International Business Machines Corporation
    Inventors: John C. Ceccherelli, Thomas M. Cowell
  • Patent number: 5537076
    Abstract: A new negative resistance circuit comprises a first N-channel enhancement FET (E-FET), an N-channel depletion FET as a load element connected to the first N-channel E-FET to form a series branch connected between negative resistance ports, and a second N-channel E-FET having source-drain path parallel to the series branch. The gate of the second N-channel E-FET is connected to the connection node between the load element and the first E-FET, while the gate electrode of the first E-FET is connected to a control port for controlling current-voltage characteristic between the negative resistance ports. The negative resistance circuit can be used in an inverter to enable the inverter to have a hysteretic function or a multivalued logic function.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: July 16, 1996
    Assignee: NEC Corporation
    Inventor: Masahiro Fujii
  • Patent number: 5365120
    Abstract: A data slicer including a comparator and a clamping circuit has been provided wherein the clamping circuit functions to clamp a signal appearing at a first input of the comparator to a predetermined voltage swing. The first input of the comparator is coupled through a capacitive element to receive an input signal. The clamping circuit includes a first diode being coupled between the first input of the comparator and a first voltage. The clamping circuit also includes a transistor having its current carrying electrodes coupled between a first supply voltage terminal and the first input of the comparator. The control electrode of the transistor is coupled to receive a second voltage. The second input of the comparator is coupled to receive a bias voltage which is substantially equal to the midpoint of the first and second voltages. The data slicer further includes a hold circuit for disabling the clamping circuit.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: November 15, 1994
    Assignee: Motorola, Inc.
    Inventor: W. Eric Main