Abstract: A laser device (100), configured for generating laser pulses, has a laser resonator (10) with a gain disk medium (11) and a Kerr medium (12). The laser resonator (10) includes a first mode shaping section (13) which is adapted for shaping a circulating electric field coupled into the gain disk medium (11), and a second mode shaping section (14), which is adapted for shaping the circulating electric field coupled into the Kerr medium (12) independently of the electric field shaping in the first mode shaping section (13). Furthermore, a method of generating laser pulses (1) using a laser resonator (10) with a gain disk medium (11) and a Kerr medium (12) is described.

Abstract: A polarization modulation device for wideband laser comprises a first polarization maintaining optical fiber, a second polarization maintaining optical fiber, and a non-polarization maintaining optical fiber. The non-polarization maintaining optical fiber includes a first polarization controller coupled with the first polarization maintaining optical fiber, and a second polarization controller coupled with the second polarization maintaining optical fiber.

Abstract: A compact optically-pumped solid-state laser designed for efficient nonlinear intracavity frequency conversion into desired wavelengths using periodically poled nonlinear crystals. These crystals contain dopants such as MgO or ZnO and/or have a specified degree of stoichiometry that ensures high reliability. The laser includes a solid-state gain media chip, such as Nd:YVO4, which also provides polarization control of the laser; and a periodically poled nonlinear crystal chip such as PPMgOLN or PPZnOLT for efficient frequency doubling of the fundamental infrared laser beam into the visible wavelength range. The described designs are especially advantageous for obtaining low-cost green and blue laser sources. Also described design of the continuously operated laser with an electro-optic element for modulation of the intensity of the laser output at frequencies up to hundred of megahertz. Such modulation is desired for various applications, including compact projectors with high resolution.

Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a substantially equivalent initial voltage. The method then includes receiving first and second clock signals. The sense amplifier is configured such that the voltage of the first node increases and the voltage of the second node decreases if the first clock signal arrives before the second clock signal. Similarly, the sense amplifier is configured such that the voltage of the second node increases and the voltage of the first node decreases if the second clock signal arrives before the first clock signal. The method may further include sampling the voltage of at least one of the first and second nodes to determine which of the first and second clock signals was the first to arrive.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: A noise injection method for characterizing common clock timing margin (jitter) includes injecting a single tone frequency, varying the amplitude of the injected frequency; measuring the signal produced at various signal amplitudes and analyzing the data obtained from measuring the signal. The obtained measurements may be analyzed using various characterizations such as measured jitter on input, measured jitter transfer, measured jitter tolerance, etc.

Abstract: A Kerr-lens mode-locked Cr:fosterite laser 15 operated with negative nonlinear phase shift. The nonlinear phase shift is induced by the cascade x(2) x(2) process in a lithium triborate crystal. Employing the cascade process at large phase mismatch produces a nearly linear frequency chirp. Transform-limited pulses as short as 60 fs are generated with positive cavity dispersion.

Abstract: A pulse detection circuit, a method of operation and a fan assembly test circuit employing the same. In one embodiment, the pulse detection circuit includes a charge pump that receives an input signal and varies a charge in a charge storage device based on the input signal. The pulse detection circuit further includes a level detector, coupled to the charge pump, that compares a voltage across the charge storage device with first and second reference voltages, and a signaling circuit, coupled to the level detector, that generates an output signal based on the comparison and indicating an existence of the pulse. The pulse detection circuit may be a part of a fan assembly test circuit adapted to receive an input signal from a cooling fan under test.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: A driver circuit in an integrated circuit includes a flip-flop circuit and a plurality of AND gates. The flip-flop circuit causes an external control signal which is supplied externally to synchronize with a clock signal, and produces an internal control signal. The AND gates control a plurality of outputs based on a data signal in accordance with the internal control signal. Since the internal control signal is synchronized with the clock signal, changes in the outputs from the AND gates are delayed from the timing of the clock signal. Thus, it is possible to prevent the occurrence of malfunction caused by a switching current to flow in transient of changes in the outputs.