Abstract: A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

Abstract: A method and apparatus for determining an amplitude-shift keying (ASK) signal, and a wireless power transmitter using the same is provided. The method of determining data of the ASK signal includes receiving a demodulated signal of a received ASK signal, measuring a pulse time during which a pulse configuring the demodulated signal is held, storing the measured pulse time, and determining information on a current pulse based on a pulse time of the current pulse of the demodulated signal and a holding time of an immediately preceding pulse.

Abstract: Provided is an image sensor configured to function as a synchronous master that controls synchronous imaging performed by a plurality of image sensors. In a case where a stop request is acquired, the image sensor stops imaging operation on the basis of the stop request, and does not transmit, to a different image sensor functioning as a synchronous slave that performs imaging under control by the synchronous master, a synchronous slave synchronous signal for controlling imaging timing of an image sensor functioning as the synchronous slave on the basis of the stop request.

Abstract: A driver chip includes a high side input terminal, a pulse generator, a level shift, a current detector, a high side output controller, and a high side output terminal. The high side input terminal receives the high side input signal and the pulse generator transfers the high side input signal into the rise pulse signal and the fall pulse signal. The current detector detects the first current and the second current flowing through the level shift, and the high side output controller generates the high side output signal. The high side output terminal controls the switching of the high side transistor by the high side output signal.

Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

Abstract: A digital input receiver system comprises a first input receiver having a first current limiter input, and a first voltage comparator input coupled to a first node. A first resistor is coupled between the first node and the first current limiter input. The first input receiver outputs a digital logic signal and is coupled to a second node. The receiver system further comprises a second input receiver having a second current limiter input, and a second voltage comparator input coupled to the second node. A second resistor is coupled between the second node and the second current limiter input. The second input receiver outputs a malfunction signal. The first and second input receivers are configured to limit current through the receiver system to less than an overcurrent threshold of the first and second input receivers.

Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

Abstract: A method and apparatus for performing operations of an electrical device, whereby the apparatus performs operations during operation of a clock producing a clock signal, asserts a reset of components performing operations for the electrical device, stops the clock through a reset generation block for a number N cycles and performs the reset of operations during the stopping of the clock through the reset generation block for the number N cycles.

Abstract: An example cement and casing evaluation tool includes an amplifier and a filter coupled an output of the amplifier. A transducer may be coupled to the output of the filter. A ringing reduction system may be coupled to at least one of the amplifier, the filter, and the transducer, wherein the ringing reduction system selectively dissipates energy from at least one of the amplifier, the filter, and the transducer in response to a control signal.

Abstract: A method of evaluating operability of a gaseous fuel admission valve of an internal combustion engine is disclosed. The method includes operating the internal combustion engine on gaseous fuel by repeatedly actuating the gaseous fuel admission valve. The method further includes measuring a sequence of temporal developments of an electrical operation parameter respectively associated with an actuation of the gaseous fuel admission valve. The sequence includes a first temporal development to be evaluated and a plurality of temporal developments preceding the first temporal development. The method also includes evaluating operability of the gaseous fuel admission valve based on the first temporal development of the measured sequence and at least one of the plurality of preceding temporal developments of the measured sequence.

Abstract: An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

Abstract: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

Abstract: The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element.

Abstract: A voltage level detector is provided. The voltage level detector includes a comparator and a threshold level changer. The comparator compares a voltage level of an increasing or decreasing input signal with a threshold level, and generates and outputs a voltage level detection signal indicating that the input signal has reached the threshold level. The threshold level changer changes the threshold level of the comparator based on the voltage level detection signal by increasing the threshold level when the input signal is monotonically increasing and decreasing the threshold level when the input signal is monotonically decreasing.

Abstract: An oscillation circuit includes: an oscillation unit which includes a first terminal and a second terminal connected to a vibrator; a third terminal to which a ground potential is supplied; a fourth terminal which is electrically connected to the second terminal, and to which at least one of an AC voltage for driving the vibrator and a voltage for operating the oscillation unit is applied; and a first switching unit which switches modes of electrical connection between the first terminal and the third terminal.

Abstract: In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.

Abstract: The present disclosure describes apparatuses and techniques for detection of an external oscillator. In some aspects, an integrated circuit includes an oscillator detector coupled to an external electrical connection. The oscillator detector may include a transistor having a gate coupled to the external electrical connection that is configured to detect a presence of an external oscillator.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.

Abstract: In response to a reset condition, the state of a steady-state signal at an I/O pin of the serial communication port of an integrated circuit die is determined. The serial communication port is configured to support one of the plurality of serial communication protocols based upon the detected steady-state condition.

Abstract: A compact optically-pumped solid-state laser designed for efficient nonlinear intracavity frequency conversion into desired wavelengths using periodically poled nonlinear crystals. These crystals contain dopants such as MgO or ZnO and/or have a specified degree of stoichiometry that ensures high reliability. The laser includes a solid-state gain media chip, such as Nd:YVO4, which also provides polarization control of the laser; and a periodically poled nonlinear crystal chip such as PPMgOLN or PPZnOLT for efficient frequency doubling of the fundamental infrared laser beam into the visible wavelength range. The described designs are especially advantageous for obtaining low-cost green and blue laser sources. Also described design of the continuously operated laser with an electro-optic element for modulation of the intensity of the laser output at frequencies up to hundred of megahertz. Such modulation is desired for various applications, including compact projectors with high resolution.

Abstract: A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal.

Abstract: The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

Abstract: A circuit including an input configured to receive a clock signal. Detection circuitry may be configured to detect if the clock signal is present on the input. An output is configured to provide a control signal having a first level if the clock signal is present on the input and a second level if the clock signal is absent from the input.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: An integrated circuit includes: a circuit pin; a detecting circuit coupled to the circuit pin, and arranged to detect a signal level value of the circuit pin when the integrated circuit operates in a first operational mode; a storage circuit coupled to the detecting circuit, and arranged to store the signal level value; and a controlling circuit coupled to the storage circuit, and arranged to set a voltage level of the circuit pin according the signal level value when a processing circuit of the integrated circuit operates in a second operational mode.

Abstract: A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A semiconductor device including an internal terminal, a first transistor of a first conductivity type that is coupled between a first reference potential and the internal terminal, and that includes a first control terminal, a second transistor of a second conductivity type that is coupled between a second reference potential and the internal terminal, and that includes a second control terminal, an oscillator that includes an output terminal to output a clock signal, and a comparator that is coupled to the internal terminal, and that compares a potential of the internal terminal when the internal terminal is coupled to the first reference potential with a potential of the internal terminal when the internal terminal is coupled to the second reference potential. Each control terminals is coupled to the output terminal to commonly receive the clock signal, and the first and second transistors exclusively operate in response to the clock signal.

Abstract: A transmission input circuit of the present invention is provided with: a current detection resistor which receives an input of a line current flowing through a transmission line and generates a line current detection voltage; a constant current circuit which generates a predetermined reference current; a first switch which performs a switching operation at an empty timing where a transmission current is not flowing, to thereby allow the reference current to flow from the constant current circuit to the current detection resistor, and generate a reference voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current; a capacitor which is connected to the current detection resistor via the first switch; a second switch which performs a switching operation in synchronization with the first switch to thereby sample-hold the reference voltage generated by the current detection resistor in the capacitor; and a comparator

Abstract: A control circuit comprising an input-output unit that is connected to a signal line, which is connected to an external apparatus, and which is connected to a resistor that is one of a pull-up resistor and a pull-down resistor; a switching unit that switches a mode of the input-output unit to one of an input mode and an output mode, wherein the output mode includes an on-voltage output mode and an off-voltage output mode; an acquisition unit that acquires information regarding whether the resistor connected to the signal line is the pull-up resistor or the pull-down resistor, when the input-output unit is in the input mode; and a control unit that controls the input-output unit to switch to one of the on-voltage output mode and the off-voltage output mode based on the acquisition information acquired by the acquisition unit, when the input-output unit is in the output mode.

Abstract: An image forming apparatus records an image on a transported recording medium. The apparatus includes a transportation unit that transports the recording medium and a recording unit that records the image on the recording medium. An encoder outputs an encoder signal including pulses according to a position of the transportation unit. A measurement unit measures a pulse period of the encoder signal, and the measured pulse period is stored by a storage unit. A detection unit detects pulse omission of the encoder signal on the basis of the value measured by the measurement unit. A pulse generation unit generates a recording timing pulse on the basis of the pulse period when the pulse omission is not detected and generates the recording timing pulse on the basis of the pulse period stored in the storage unit and measured before the pulse omission when the pulse omission is detected.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a waveform. The MCS3P simultaneously produces square wave, Gaussian, and monocycle waveforms by differentiating a sinusoidal source. The method includes the steps of compressing the rising edge of a sinusoidal source waveform, differentiating the resulting waveform to form a square waveform and a Gaussian waveform, filtering out the positive going Gaussian to produce a negative going Gaussian, differentiating the Gaussian waveform to form a monocycle waveform, and compressing the falling edge of the square waveform to produce a square wave form with both edges compressed.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: A circuit for preventing a setup fail between a first latch and a second latch according to one embodiment of the present invention comprises a mimic combinational logic module and a clock compare module. The mimic combinational logic module is configured to receive a first clock signal for the first latch and to generate a delayed first clock signal, which is a delayed version of the first clock signal. The clock compare module is configured to provide a delayed second clock signal, which is a delayed version of a second clock signal for the second latch, to the second latch after receiving the delayed first clock signal and the second clock signal.

Abstract: Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.

Abstract: A pulse signal generating device includes: an encoder that outputs a pulse with a period corresponding to the speed of an object to be detected; a measurement unit that measures a period of the pulse; a storage unit that stores the measured period; an operation unit that calculates a reasonable period, which is estimated to be statistically reasonable, on the basis of a result of period measurement of a plurality of pulses; a detection unit that detects period abnormalities when the measured period of the measurement unit satisfies a period abnormality condition specified from the reasonable period; and a pulse generating unit that generates a pulse on the basis of the measured period when the period abnormalities are not detected and generates a pulse on the basis of the reasonable period when the period abnormalities are detected.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.

Abstract: A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.